3nm-Process

A label shared by different transistor choices. A 3nm process denotes a supplier’s advanced logic generation, rather than a common physical gate dimension. The generation is especially useful for understanding why node names cannot specify transistor architecture: TSMC’s N3 family uses FinFETs, while Samsung introduced a 3nm-class gate-all-around platform. Both descriptions can be correct because each supplier defines its own process family and qualification milestones.

FinFET and nanosheet approaches. A FinFET gate controls a vertical silicon fin from multiple surfaces. A nanosheet gate-all-around device surrounds released horizontal channels, providing another route to electrostatic control. Neither device shape alone establishes product superiority. Channel dimensions, contacts, parasitic capacitance, wiring resistance, cell architecture, and operating voltage combine to determine the behavior that a circuit designer actually receives.

Production milestones need attribution. TSMC identifies 2022 as the start of high-volume N3 FinFET production. Samsung announced initial production of its GAA-based 3nm process on June 30, 2022. Initial production, a mature volume ramp, and broad customer adoption are separate milestones. These dated statements establish different company events; they do not establish identical capacity, yield, or commercial readiness across the two suppliers.

Families extend beyond their first release. A node can acquire enhanced, performance-oriented, automotive, or cost-oriented derivatives. Such extensions may change libraries and design rules as well as process steps. A design that targets one variant cannot automatically be assigned the characteristics of every other member. Comparisons should identify the exact release, the relevant PDK, and the standard-cell or SRAM configuration used for the measurement.

System-level tradeoffs remain decisive. Denser logic can increase the number of functions in a die, but memory bandwidth, heat removal, supply integrity, and packaging may constrain useful throughput. Analog functions and external interfaces may remain on other processes. Evaluating a 3nm product therefore requires its workload, package, power envelope, and manufacturing maturity alongside the lithography and transistor technology used to build it.

Sources and further reading. [TSMC logic technology](https://www.tsmc.com/english/dedicatedFoundry/technology/logic/l_3nm); [Samsung June 2022 production announcement](https://news.samsungsemiconductor.com/global/samsung-begins-chip-production-using-3nm-process-technology-with-gaa-architecture/).

Read 3nm process as a process-generation label that requires a vendor, variant, and measured implementation to become specific.