Advanced CMOS Scaling 2000s Integrate Tensile Capping Layers for Nmos Strain

# Advanced CMOS Scaling (2000s): Step 9 — Integrate Tensile Capping Layers for Uniaxial NMOS Strain

## 1. The NMOS Counterpart to Embedded SiGe

Step 7 showed that NMOS channels need tensile, not compressive, strain to gain electron mobility — the opposite sign from the PMOS technique in Step 8 — so embedding a larger-lattice-constant alloy into the NMOS source/drain would be counterproductive. The production technique used for NMOS instead applies strain from outside the transistor entirely: a silicon nitride film deposited over the already-completed device with deliberately engineered high intrinsic tensile stress, commonly called a tensile contact etch-stop layer (CESL) or stress liner.

## 2. Repurposing an Existing Process Step for a New Physical Effect

Contact etch-stop layers were already a standard part of the interconnect flow, used to protect the underlying transistor during the etch that opens contact holes down to source, drain, and gate. Process engineers found that depositing this same layer under conditions that gave it a strong intrinsic tensile stress — through deposition temperature, gas chemistry, and post-deposition UV or thermal treatment — caused the film's own tendency to contract to pull the silicon channel directly beneath it into tensile strain, delivering the mobility gain Step 7 predicted without requiring any change to the transistor's own source/drain structure.

## 3. A Strain Technique That Is Easy to Apply Selectively

Because the tensile capping layer is deposited after the transistor is complete, across the whole wafer, it can be selectively removed from PMOS regions (where tensile strain would work against the compressive strain Step 8 already delivers there) using a masked etch, leaving the tensile film only over NMOS devices. This selective-masking capability is exactly what makes combining both strain techniques on a single die possible — and exactly what makes doing so a genuine integration challenge, the subject of Step 10.

A Tensile Capping Layer Stretches the NMOS Channel tensile strain delivered into the channel versus stressed-nitride capping-layer intrinsic stress tensile strain delivered into the channel (rises with the capping layer's own intrinsic stress) unstrained baseline, no capping layer applied a highly tensile-stressed nitride film pulls the channel it sits atop into tension capping layer intrinsic tensile stress increases left to right the stress is deposited over the already-completed transistor, not built into its source/drain this is the NMOS-specific counterpart to Step 8's PMOS-specific embedded SiGe technique
Tensile Capping Layer Deposition Over a Completed NMOS Device how a stressed film placed on top of the transistor strains the channel beneath it COMPLETED NMOS GATE Si Substrate Channel Tension Stressed Nitride Cap transistor is finished through contact formation before the capping film is added TENSILE NITRIDE DEPOSITION Si Substrate Channel Tension Stressed Nitride Cap a silicon nitride film with high intrinsic tensile stress is deposited as a contact etch-stop layer CHANNEL TENSION Si Substrate Channel Physical Feature Layer Process Architecture the film's own tendency to contract pulls the underlying channel into tensile strain Key Semiconductor Engineering Takeaway the same film also serves its original purpose as a contact etch-stop layer — the strain effect is a bonus

Take advanced cmos scaling 2000s integrate tensile capping layers for nmos strain further

Ask the copilot about this term, or have our engineers assess it against your process.

Ask CFSGPT about this → Request a technical assessment → Open the CFS app