atomic layer etching
**Atomic Layer Etching (ALE)** is the **technique that removes material one atomic layer at a time using self-limiting surface reactions** — providing angstrom-level precision for critical patterning at advanced technology nodes where conventional reactive ion etching lacks the control needed for sub-5nm feature dimensions.
**How ALE Works**
**Two-Step Cycle**:
- **Step 1 — Modification**: Reactive gas (Cl2, BCl3) chemisorbs onto the surface, modifying exactly one atomic layer. Reaction is self-limiting — excess gas does not penetrate deeper.
- **Step 2 — Removal**: Low-energy ion bombardment (Ar+, typically 10–25 eV) sputters only the modified layer, leaving underlying material intact.
- **Purge** between steps removes by-products and excess reactants.
- Each cycle removes ~0.3–0.5 angstrom of material.
**ALE vs. Conventional Etching**
| Parameter | RIE/Plasma Etch | Atomic Layer Etch |
|-----------|-----------------|-------------------|
| Control | ~1 nm at best | 0.3–0.5 Å per cycle |
| Damage | Ion bombardment damage | Minimal (low energy ions) |
| Selectivity | Material-dependent | Extremely high (self-limiting) |
| Throughput | Fast (seconds) | Slow (minutes per nm) |
| Uniformity | Limited by plasma uniformity | Inherently uniform |
**Types of ALE**
- **Directional (Anisotropic) ALE**: Ion bombardment provides directionality — used for gate trimming, fin thinning.
- **Isotropic (Thermal) ALE**: Chemical removal without ion bombardment — used for selective material removal in 3D structures like nanosheet inner spacers.
**Applications at Advanced Nodes**
- **FinFET fin width trimming**: Sub-nm precision on fin width for Vt control.
- **Nanosheet channel thinning**: Precise channel thickness control.
- **Self-aligned contact etch**: Controlled recess without punching through thin etch stops.
- **EUV resist trimming**: Smoothing line edge roughness by controlled atomic-scale removal.
Atomic layer etching is **the etch counterpart to ALD** — together they define the atomic-precision processing paradigm that makes sub-3nm transistor fabrication possible.