ale self limited kinetics
Atomic Layer Etching is the leading-edge subtractive nanofabrication technology that utilizes sequential, self-limiting surface modification and volatile desorption half-reactions to remove material layer-by-layer with sub-angstrom depth precision and near-infinite material selectivity. As semiconductor scaling advances into sub-2nm Gate-All-Around nanosheets and 3D memory architectures, conventional continuous reactive ion etching causes unacceptable atomic lattice damage, microloading, profile bowing, and severe aspect-ratio-dependent etching lag. ALE resolves these challenges by decoupling chemical reactant adsorption from reaction product removal, enabling perfect depth control, sub-nanometer roughness, and damage-free etching across both directional plasma and isotropic thermal regimes.
**Self-limiting half-reactions govern layer-by-layer digital removal in atomic layer etching.** In classic reactive ion etching (RIE), chemical etching radicals and energetic ions strike the wafer surface simultaneously, creating continuous, uncontrollable etching profiles susceptible to microloading and micro-trenching. ALE replaces this continuous regime with two distinct, self-limiting steps comprising surface modification (where reactive halogens like $\text{Cl}_2$ or $\text{NF}_3$ chemisorb and alter the topmost 1 to 2 atomic layers) followed by product desorption (where low-energy $\text{Ar}^+$ ions or thermal ligand-exchange vapors selectively desorb the modified layer and abruptly halt).
**ALE synergy defines the degree of self-limiting ideality and process controllability.** The performance of an atomic layer etching process is quantified by the dimensionless ALE Synergy metric ($S$):
$$
S = \frac{\text{EPC}_{\text{ALE}} - (\text{EPC}_{\text{mod}} + \text{EPC}_{\text{des}})}{\text{EPC}_{\text{ALE}}}.
$$
Here, $\text{EPC}_{\text{mod}}$ is the spontaneous chemical etch rate during the modification pulse alone, and $\text{EPC}_{\text{des}}$ is the physical sputtering rate during the desorption pulse alone. An ideal ALE process achieves $S \approx 1.0$ ($> 95\%$), ensuring that neither half-step causes material removal independently and that etching occurs strictly through synergistic two-step reaction pairing.
**Directional plasma ALE exploits the ion energy window between desorption and sputtering.** In directional plasma ALE, anisotropic feature profiles are achieved by directing low-energy $\text{Ar}^+$ ions perpendicular to the wafer substrate. Process engineers operate strictly within the "ALE energy window" bounded by the chemical desorption threshold energy ($E_{\text{des}} \approx 20\text{--}30\text{ eV}$) and the physical sputtering threshold energy ($E_{\text{sputter}} \approx 50\text{--}60\text{ eV}$). Operating below the sputtering threshold ensures zero physical damage, zero mask erosion, and infinite selectivity to underlying stopping layers.
**Thermal isotropic ALE uses sequential fluorination and ligand-exchange coordination chemistry.** For complex 3D nanostructures requiring uniform isotropic lateral recess, thermal ALE operates entirely without energetic plasma ions. In the thermal ALE of aluminum oxide ($\text{Al}_2\text{O}_3$), hydrogen fluoride ($\text{HF}$) fluorinates the oxide surface into an aluminum fluoride ($\text{AlF}_3$) layer. In the subsequent step, a metal-organic precursor such as Trimethylaluminum ($\text{Al(CH}_3)_3$) or Tin(II) acetylacetonate ($\text{Sn(acac)}_2$) undergoes transmetalation ligand exchange, reacting with $\text{AlF}_3$ to form volatile organometallic compounds ($\text{AlF(CH}_3)_2\uparrow$) that vaporize into the vacuum exhaust.
| ALE Process Module | Reactant Pairing | Operating Temperature | Etch Per Cycle (EPC) | Etch Selectivity | Primary Semiconductor Implementation |
|---|---|---|---|---|---|
| Directional Silicon ALE | $\text{Cl}_2\ \text{adsorption} + \text{Ar}^+\ \text{ions (30 eV)}$ | Room Temp ($20^\circ\text{C}\text{--}60^\circ\text{C}$) | $0.6\text{--}1.0\text{ \AA/cycle}$ | $> 100:1$ to $\text{SiO}_2/\text{Si}_3\text{N}_4$ | FinFET & GAA fin trimming and gate recess |
| Directional Dielectric ALE | $\text{C}_4\text{F}_8/\text{Ar}\ \text{deposition} + \text{Ar}^+\ \text{activation}$ | $20^\circ\text{C}\text{--}80^\circ\text{C}$ | $0.4\text{--}0.8\text{ \AA/cycle}$ | $> 50:1$ $\text{SiO}_2$ over $\text{Si}_3\text{N}_4$ | Self-Aligned Contact (SAC) hole opening |
| Thermal Isotropic $\text{Al}_2\text{O}_3 / \text{HfO}_2$ | $\text{HF} / \text{XeF}_2 + \text{Al(CH}_3)_3 / \text{Sn(acac)}_2$ | $150^\circ\text{C}\text{--}300^\circ\text{C}$ | $0.5\text{--}1.2\text{ \AA/cycle}$ | Near-infinite to $\text{Si} / \text{SiO}_2$ | High-k gate dielectric recess & cleanup |
| Sacrificial $\text{SiGe}$ Cavity Recess | $\text{CF}_4/\text{O}_2\ \text{radicals} + \text{organic vapor}$ | $60^\circ\text{C}\text{--}120^\circ\text{C}$ | $0.8\text{--}1.5\text{ \AA/cycle}$ | $> 150:1\ \text{SiGe}:\text{Si}$ | GAA nanosheet inner spacer cavity formation |
| Metal ALE ($\text{Cu} / \text{Ru} / \text{Co}$) | $\text{Cl}_2 / \text{O}_2\ \text{oxidation} + \text{hfac / acetylacetone}$ | $120^\circ\text{C}\text{--}250^\circ\text{C}$ | $0.3\text{--}0.6\text{ \AA/cycle}$ | $> 80:1$ to dielectrics | Dual Damascene via bottom clean & 3D packaging |
**Atomic layer etching eliminates aspect-ratio-dependent etching lag across deep nanostructures.** In conventional reactive ion etching of high-aspect-ratio holes and trenches ($AR > 40:1$), neutral Knudsen diffusion throttling starves deep feature floors of chemical etchants, causing narrow trenches to etch far slower than wide fields. Because ALE utilizes extended precursor saturation exposure times during the modification phase, every atomic site—regardless of trench depth or feature pitch—reaches $100\%$ chemical saturation. Consequently, etch per cycle remains completely uniform across all pattern geometries, eliminating ARDE lag and microloading.
```flowchart
st=>start: Heat wafer in vacuum chamber to calibrated process temperature
gas_mod=>operation: Pulse reactive modification gas (Cl2 / HF) to form self-limiting surface monolayer
purge_a=>operation: Inert gas purge clears unreacted chemical vapors and volatile precursors
desorp_pulse=>operation: Apply energetic stimulus (low-energy Ar+ ions <50eV or ligand-exchange vapor)
desorp_react=>operation: Self-limiting desorption of modified top atomic layer halts abruptly upon completion
purge_b=>operation: Inert gas purge sweeps desorbed reaction byproducts into vacuum exhaust
cycle_check=>operation: Repeat N cycles to achieve target sub-angstrom etch depth with zero ARDE lag
pass=>end: Atomically smooth, damage-free etched cavity ready for subsequent deposition
st->gas_mod->purge_a->desorp_pulse->desorp_react->purge_b->cycle_check->pass
```
**Mastering sub-2nm architectural scaling requires treating material removal through a self-limiting-surface-chlorination-ion-synergy-and-thermal-ligand-exchange lens.** By uniting gaseous chemisorption saturation thermodynamics, sub-sputtering ion energy window control, thermal coordination transmetalation kinetics, and zero-lag feature scaling, semiconductor foundries achieve atomic-level manufacturing precision. Mastering ALE kinetics ensures that GAA nanosheet channels, inner spacer cavities, self-aligned contact vias, and advanced 3D memory arrays achieve flawless geometric fidelity, atomic surface smoothness, and exceptional device reliability across billions of nanoscale transistors.