back-end-of-line (beol) scaling

Back-end-of-line (BEOL) scaling reduces metal interconnect pitch and improves wiring density to match the increasing transistor density from front-end scaling. BEOL structure: multiple metal layers (10-15+ at advanced nodes) with increasing pitch from bottom (local interconnect, M1-M2) to top (global wiring, power distribution). Scaling challenges: (1) Resistance increase—Cu resistivity rises dramatically below ~30nm line width due to grain boundary and surface scattering; (2) Capacitance—tighter spacing increases coupling capacitance despite low-κ dielectrics; (3) RC delay—interconnect delay dominates over gate delay at advanced nodes; (4) Reliability—electromigration worsens with smaller cross-sections and higher current density. Metal pitch progression: 90nm node (~280nm M1P) → 7nm (~36nm) → 3nm (~21nm) → 2nm (~16nm target). Resistance mitigation: (1) Tall, narrow lines—maximize cross-section; (2) Cobalt or ruthenium for narrow lines (lower resistivity at small dimensions than Cu due to shorter mean free path); (3) Barrier-less or thin-barrier integration—maximize Cu volume; (4) Subtractive etch—avoid conformal barrier overhead of damascene. Capacitance reduction: low-κ dielectrics (SiOCH, κ ≈ 2.5-3.0), air gap integration (κ = 1.0), self-aligned patterning for tighter pitch control. Patterning: EUV single-patterning for ~28-36nm pitch, EUV double-patterning for sub-28nm, SAQP for tightest pitches. Via resistance: semi-damascene or subtractive via approaches to reduce via resistance at tight pitches. BEOL scaling is now the primary bottleneck limiting chip performance and density scaling at advanced nodes.