back-end-of-line integration

**BEOL** (Back-End-of-Line) Integration is the **fabrication of the multi-level metal interconnect stack above the transistors** — building 10-15+ layers of copper wires and vias in low-k dielectric that route signals, power, and clock across the chip. **BEOL Process Sequence (per layer)** - **Dielectric Deposition**: Deposit low-k ILD (SiCOH, $k$ ≈ 2.5-3.0). - **Patterning**: Lithography and etch of trenches (wires) and vias (vertical connections). - **Barrier/Seed**: Deposit TaN/Ta barrier + Cu seed layer by PVD. - **Cu Fill**: Electroplate copper to fill trenches and vias. - **CMP**: Planarize excess copper — dual-damascene process. **Why It Matters** - **RC Delay**: BEOL wire RC delay increasingly dominates total chip delay at advanced nodes. - **Power Delivery**: Power distribution network through BEOL must deliver >100A at <1V with minimal IR drop. - **Reliability**: Electromigration, stress migration, and TDDB in BEOL are critical reliability concerns. **BEOL** is **the highway system of the chip** — building layer upon layer of copper highways that carry signals and power across billions of transistors.