beol process
**BEOL (Back End of Line)** — the portion of chip fabrication that creates the multilayer metal interconnect stack connecting transistors to each other and to I/O pads, after transistor formation is complete.
**What BEOL Includes**
- Contact/via layers: Connecting transistors to first metal
- Metal layers (M1 through M10–M15): Copper wires of increasing pitch
- Inter-metal dielectrics (low-k materials)
- Passivation and pad formation
**BEOL Layer Structure**
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**Key BEOL Processes**
- Dual damascene copper metallization
- Low-k dielectric deposition and curing
- CMP at every metal level
- Barrier/seed deposition (PVD)
- Electroplating (ECD)
**BEOL Scaling Challenge**
- Wire resistance increases as pitch shrinks (surface/grain boundary scattering)
- RC delay of wires now dominates over transistor delay
- BEOL contributes 50–70% of total chip delay at advanced nodes
**BEOL** accounts for ~60% of all fabrication process steps and is increasingly the performance bottleneck — interconnect innovation is as critical as transistor innovation.