Bspdn Form Nano Through Silicon Vias to Transistor Contacts

# Backside Power Delivery: Step 7 — Form Nano-Through-Silicon-Vias to the Transistor Contacts

## 1. Not an Ordinary Through-Silicon-Via

Package-level through-silicon-vias used in conventional 3D stacking are measured in microns
across. Nano-TSVs, by contrast, are a different scale of structure entirely -- a few hundred
nanometers in diameter, with high aspect ratios, because they must land precisely on a buried
power rail that may itself be only tens of nanometers wide, after etching through the thinned
backside membrane Step 6 exposed.

## 2. The Etch and Fill Sequence

Forming a nano-TSV starts with backside lithography to pattern via locations with nanometer-
scale alignment accuracy to the buried structures beneath. A high-aspect-ratio etch then
opens a narrow channel through the thinned silicon membrane, stopping on or very near the
buried power rail. A barrier and liner are deposited to prevent metal diffusion into the
silicon, and the via is filled with a low-resistance conductor to complete the electrical path.

## 3. Why Diameter Is a Genuine Tradeoff

Via resistance rises sharply as diameter shrinks -- narrower vias are desirable for density but
directly fight the drive to keep resistance low enough that the nano-TSV does not reintroduce
the very voltage-drop problem BSPDN exists to solve. Foundries balance this by keeping power
vias deliberately wider than would be dictated by density alone, accepting a modest area cost
in exchange for a resistance budget the power network can tolerate.

## 4. Landing on the Transistor's Source and Drain

The nano-TSV's ultimate destination is not the transistor gate but its source and drain
contacts, delivering power directly to the terminals that actually draw current, by way of the
buried power rail Step 8 introduces next. This directness -- power reaching the active
terminals from below rather than routed down through many frontside layers -- is the structural
basis for the IR-droop reduction this series quantifies in Step 10.

Nano-TSV: Etch, Liner, and Fill Through the Thinned Membrane a high-aspect-ratio via connecting backside metal to a buried power rail BACKSIDE METAL: ENTRY POINT FOR THE NANO-TSV Transistor / Channel Layer Thinned Substrate / Via Field THINNED MEMBRANE: ETCHED, LINED, AND FILLED FOR THE VIA Power Trunk Return Trunk Signal Power via diameter and via resistance pull in opposite directions by design the via lands on a buried power rail only tens of nanometers wide
Backside Power Delivery: Step 7 — Form Nano-Through-Silicon-Vias to the Transistor Contacts Interconnect decoupling, nano-TSV/buried power rails, and standard-cell scaling NOT AN ORDINARY THROUGH-SI... Thinned Si Substrate <500nm Transistor S/D nTSV Sub-50nm Nano-TSV Package-level through- silicon-vias used in conventional 3D stacking are measured in microns across. THE ETCH AND FILL SEQUENCE Thinned Si Substrate <500nm Frontside Signal M0-M6 Backside Power B0-B3 Backside Power Delivery Forming a nano-TSV starts with backside lithography to pattern via locations with nanometer- scale alignment accuracy to the buried structures beneath. WHY DIAMETER IS A GENUINE ... Thinned Si Substrate <500nm Frontside Signal M0-M6 Backside Power B0-B3 Backside Power Delivery Via resistance rises sharply as diameter shrinks -- narrower vias are desirable for density but directly fight the drive to keep resistance low enough that Key Semiconductor Engineering Takeaway BSPDN Step 7 uncouples power delivery from signal routing to resolve advanced node interconnect bottlenecks. Essential companion architecture deployed across 2nm and sub-2nm nodes by Intel, TSMC, and Samsung.

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