Bspdn Integrate Buried Power Rails Beneath Transistor Layer

# Backside Power Delivery: Step 8 — Integrate Buried Power Rails Beneath the Transistor Layer

## 1. Sinking the Rail Below the Device

The buried power rail (BPR) is the frontside-side half of the BSPDN interface: instead of
running VDD and VSS as ordinary metal wires above the transistor the way conventional
interconnect does, the rail is sunk into a trench below the active device layer, formed during
frontside processing long before the wafer is ever flipped.

## 2. Material Choice Is Driven by Thermal Survival

Buried power rails are typically formed from refractory metals -- ruthenium or tungsten are
commonly discussed choices -- selected specifically because they must survive the full
remaining frontside thermal budget: every high-temperature anneal and junction-formation step
that happens after the rail is buried but before the transistor is finished. A rail material
that could not tolerate those temperatures would degrade or diffuse before the chip was even
complete.

## 3. Contacted From Beneath, Not Above

Because the rail sits below the device layer rather than above it, it is reached from beneath
-- by the nano-TSV formed in Step 7, after the wafer has been flipped and thinned -- rather
than by a via descending from the frontside signal stack. This is the physical point where the
"backside" and "frontside" halves of BSPDN actually meet.

## 4. Removing Rails From the Cell's Metal Budget

Before BPR adoption, a standard cell's lowest metal layers had to devote routing tracks to
power rails running alongside signal wires. Sinking the rail below the device removes that
allocation from the cell's frontside metal budget entirely -- the direct mechanism behind the
standard-cell area shrink this series quantifies in Step 11, and a change that happens whether
or not the rest of BSPDN's backside metal and nano-TSVs are present.

Buried Power Rail: Sunk Below the Transistor, Contacted From Below a refractory-metal rail formed during frontside processing, before any wafer flip ACTIVE DEVICE LAYER: TRANSISTORS ABOVE THE RAIL Transistor / Channel Layer Thinned Substrate / Via Field BURIED POWER RAIL: REFRACTORY METAL TRENCH BELOW THE DEVICE Power Trunk Return Trunk Signal Power the rail survives every frontside thermal step that follows its formation contacted from beneath by the nano-TSV once the wafer is flipped and thinned
Backside Power Delivery: Step 8 — Integrate Buried Power Rails Beneath the Transistor Layer Interconnect decoupling, nano-TSV/buried power rails, and standard-cell scaling SINKING THE RAIL BELOW THE... Thinned Si Substrate <500nm Active Fin / Sheet Buried Rail (Ru/W) BPR Embedded in STI The buried power rail (BPR) is the frontside-side half of the BSPDN interface: instead of running VDD and VSS as ordinary metal wires above the transistor the way MATERIAL CHOICE IS DRIVEN ... Thinned Si Substrate <500nm Heat Flux Path Thermal Dissipation Buried power rails are typically formed from refractory metals -- ruthenium or tungsten are commonly discussed choices -- selected specifically CONTACTED FROM BENEATH, NO... Thinned Si Substrate <500nm Transistor S/D nTSV Sub-50nm Nano-TSV Because the rail sits below the device layer rather than above it, it is reached from beneath -- by the nano-TSV formed in Step 7, after the wafer has been flipped and Key Semiconductor Engineering Takeaway Buried power rails (BPR) embedded in shallow trench isolation deliver supply current directly from below the channel. Eliminates power delivery vias from the crowded frontside stack and enables 20-30% standard cell area reduction.

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