Bicmos Logic 1980s Confront the CMOS Drive Current Limit

# BiCMOS Logic (Late 1980s): Step 1 — Confront CMOS's Drive-Current Limit at the Output Pin

## 1. Where CMOS Logic Runs Out of Push

By the mid-1980s, CMOS had already won the static-power argument this project traced through the `cmos_logic_1980s` series — near-zero quiescent current, a full-rail noise margin, and density that kept scaling as geometries shrank. But a single CMOS inverter's output stage is sized by the same small transistors that make the gate itself dense and low-power, and that same sizing becomes a liability the moment the output has to drive something large: a long bus line, an off-chip pad, a heavily loaded clock tree, or the input of many parallel gates at once. A minimum-size CMOS pull-up or pull-down transistor can source or sink only a modest current before its own channel resistance and limited transconductance become the bottleneck, and charging a large external capacitance through that resistance takes time that scales directly with how much capacitance sits on the output.

## 2. Why Making the Transistors Bigger Doesn't Fully Solve It

The obvious fix — widen the output transistors — works, but only partially and at a cost. A MOSFET's drive current scales with gate width, so a wider device sinks or sources more current, but the gate capacitance the *previous* stage must now drive also scales with that same width, pushing the loading problem one stage upstream instead of eliminating it. Widening every output stage in a long logic chain to fix the last stage's load means paying area and input capacitance at every stage along the way, and MOSFET drive current only scales linearly with width while gate capacitance scales the same way — there is no free multiplier available from sizing alone. Bipolar ECL logic, covered in `bipolar_ecl_1960s_step01` through its full series, solved exactly this drive problem over a decade earlier by using a device whose current gain lets a small base current control a much larger collector current — the question this series opens is whether that same bipolar output strength can be grafted onto a CMOS gate without giving up CMOS's density and static-power advantages for the chip as a whole.

## 3. Companion Diagram One: Quantitative View

Where the CMOS Pull-Down Runs Out of Current output fall time against load capacitance, single CMOS inverter fall time, minimum-size CMOS output fall time, widened CMOS output both curves rise with load — neither is free small device: cheap, but slow past a modest load wider device: faster, but costs input capacitance upstream t_fall ~ C_L / I_D(sat) — drive current is the limited resource widening the device moves the cost, it does not remove it

## 4. Companion Diagram Two: Structural View

One Output Pin, Three Loads It Must Drive the same CMOS output stage against three real loads ON-CHIP GATE small C_L, CMOS wins easily LONG BUS LINE large distributed C_L, CMOS slows sharply OFF-CHIP PAD largest C_L, CMOS struggles most the drive-current limit is a load-dependent problem, not a universal one

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