Bipolar Ecl 1960s Trace Propagation Delay Through the Gate
# Bipolar ECL Logic (1960s): Step 9 — Tracing Propagation Delay Through the Gate
Where every nanosecond of ECL gate delay actually comes from. Earlier steps established qualitatively that avoiding saturation (Step 3) and keeping logic swings small (Step 5) both help speed. This step adds up the actual delay contributors in a 1960s ECL gate quantitatively, as a foundation for the TTL comparison in Step 10 and the power-delay tradeoff in Step 11.
## 1. The Delay Chain: Input to Output
A signal entering an ECL current switch encounters, in sequence: the base-emitter junction's intrinsic transit time (the time for carriers to cross the base and depletion regions, set by the transistor's f_T — typically corresponding to a transit time of a few hundred picoseconds for the double-diffused and early epitaxial planar bipolar transistors used in 1960s ECL); the time to charge the collector-node parasitic capacitance through the available switching current, roughly C·ΔV/I where ΔV is the roughly 0.8 V logic swing and I is the emitter-current-source value; and the emitter follower's own transit time and its output-node charging time against whatever capacitive load (trace plus fan-out) it is driving. None of these steps involves waiting for stored charge to recombine, because none of the transistors saturate — the entire delay chain is transit-time- and capacitance-charging-limited.
## 2. Real Diagram: Gate Delay Breakdown by Contributor
## 3. Why the Breakdown Matters for Design
Because each term in the delay chain is either an intrinsic transistor property (transit time, essentially fixed once the process is chosen) or a C·ΔV/I charging term that the designer can trade against power (more current I charges a given capacitance faster but draws more supply power continuously, per Step 2's observation that ECL current draw does not depend on logic state), ECL gate delay becomes a design knob rather than a fixed property of the logic family. 1960s MECL-generation parts typically specified propagation delays in the 2-4 nanosecond range per gate; later MECL II and MECL 10K generations (Steps 16-17) pushed the same topology to sub-nanosecond and then back toward lower power at modestly higher delay, illustrating that the delay chain identified here is what every subsequent MECL generation was optimizing against.
## 4. Companion Diagram: Stage Sequence and Trend Summary
## Tracing Propagation Delay Through the Gate's Place in the Process Lineage
This is step 9 of 20 in the Bipolar ECL Logic (1960s) series, breaking propagation delay down into its transit-time and capacitance-charging contributors as the basis for the family-generation and TTL comparisons that follow.