Cfet Logic Establish Vertical Device Stacking as the Remaining Scaling Axis

# CFET (Complementary FET): Step 2 — Establish Vertical Device Stacking as the Remaining Scaling Axis

## 1. The Core Structural Move

CFET's defining change is simple to state and hard to build: take an n-type nanosheet device and a p-type nanosheet device — the same two device types that sit side by side in every standard cell today — and place one directly above the other in the same vertical column, so the pair occupies one device footprint instead of two. The bottom device and the top device each keep their own released, gate-wrapped channel sheets (the same unit processes `gaa_nanosheet_2020s` Steps 5-7 cover), but the two stacks now sit on top of each other rather than beside each other.

## 2. Why This Specific Pairing

Logic gates are built from complementary pairs of n-type and p-type transistors by construction — that is what "complementary" in CMOS means, and it is why an inverter needs exactly one of each. Stacking the n-type and p-type devices of that same complementary pair, rather than stacking two devices of the same type, means the stack height corresponds directly to one logic function's device count, not an arbitrary doubling. This is also why the convention adopted across the research literature and followed in this series places the n-type (NMOS) device on the bottom and the p-type (PMOS) device on top — a choice driven by which device's source/drain epitaxy and contact scheme is easier to process first, discussed further in Steps 5-7.

## 3. What This Does to Standard-Cell Area

If a cell's two complementary transistors no longer sit side by side at all, the cell's width — the lateral dimension that forksheet and nanosheet-count sizing (`gaa_nanosheet_2020s` Steps 9-10) have both been used to compress — no longer needs to accommodate two separate devices in the same row. In principle, a cell built from a CFET stack can approach half the standard-cell area of the equivalent side-by-side nanosheet cell, for the simplest logic functions. Step 13 of this series walks through exactly why that halving holds for the inverter case specifically, and where it breaks down for more complex gates.

## 4. Two Ways to Build the Stack

Nothing about "stack one device on top of another" specifies how the physical fabrication sequence actually gets there. Two distinct integration philosophies have emerged in the research literature — monolithic CFET, which grows and processes both devices in one continuous sequence on a single wafer, and sequential CFET, which finishes the bottom device first and bonds a second, separately processed wafer or layer on top for the top device. Steps 5-7 of this series take up that distinction as CFET's first genuinely hard integration choice.

Side-by-Side Versus Stacked: The Same Complementary Pair an inverter's NMOS/PMOS pair, laid out two different ways NANOSHEET GAA: SIDE BY SIDE NMOS PMOS full width: two device footprints CFET: STACKED PMOS (top) NMOS (bottom) one device footprint, same two transistors the same complementary NMOS/PMOS pair every logic gate already needs, placed on a new axis
Two Integration Philosophies, One Goal monolithic and sequential CFET both reach the same stacked structure MONOLITHIC one continuous build sequence, one wafer, thermal budget shared across both devices SEQUENTIAL bottom device finished first, second wafer bonded on top for the top device Steps 5-7 of this series weigh both paths and their distinct tradeoffs in depth

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