Cfet Logic Walk Through Why Vertical Stacking Halves Standard Cell Height

# CFET (Complementary FET): Step 12 — Walk Through Why Vertical Stacking Halves Standard-Cell Height

## 1. Cell Height, Defined

A standard cell's height is the vertical dimension of its footprint as laid out in a digital design — the dimension measured perpendicular to the cell rows a placement tool stacks on top of each other to fill a chip. In a side-by-side nanosheet inverter, the NMOS device sits in one horizontal track of the cell and the PMOS device sits in an adjacent horizontal track, so the cell's height has to be tall enough to contain both device rows plus the routing and isolation between them.

## 2. Why a CFET Inverter Needs Only One Device Row's Worth of Height

Because the CFET inverter's NMOS and PMOS devices occupy the same horizontal footprint, stacked vertically in the direction perpendicular to the chip's surface rather than within the chip's own layout plane, the cell's height in the layout plane only has to accommodate one device row, not two. The second device's silicon now sits in a dimension the 2D standard-cell layout grid does not measure at all — the stack height becomes a fabrication-process parameter, not a layout-area parameter. This is the direct mechanism behind the area halving Steps 1-2 described only in outline.

## 3. A Concrete Comparison

Picture a side-by-side nanosheet inverter cell with an NMOS row and a PMOS row, each requiring its own routing track for power, ground, and signal access, plus the lateral isolation spacing between the two rows. A CFET inverter built on the same process node needs only one row's worth of those same elements in the layout plane, because the two devices' tracks are now stacked rather than laid side by side. Approaching half the cell height — and therefore, for a cell whose width is otherwise unchanged, approaching half the cell area — is the direct consequence, not a separate additional benefit requiring its own explanation.

## 4. Where the Simple Halving Argument Starts to Break Down

The clean halving argument above holds cleanly for the inverter precisely because the inverter needs exactly one NMOS device and one PMOS device, matching CFET's one-on-one stacking unit exactly. Logic gates needing more than one device of a given type per cell — a two-input NAND needs two series NMOS devices and two parallel PMOS devices — do not map onto a single CFET stack as cleanly, and Step 16 of this series takes up directly how and whether the same halving logic extends to those more complex gates.

Cell Height: Two Rows Versus One the same inverter, laid out side by side and stacked NANOSHEET INVERTER PMOS row NMOS row full cell height CFET INVERTER both devices, one row half the height the second device moves out of the layout plane entirely — into the fabrication process, not the layout grid
Where the Clean Halving Argument Holds the inverter's 1-NMOS/1-PMOS structure matches CFET's stacking unit exactly INVERTER 1 NMOS + 1 PMOS maps exactly onto one CFET stack 2-INPUT NAND 2 series NMOS + 2 parallel PMOS does not map onto one stack as cleanly Step 16 takes up exactly how far the halving logic extends past the inverter case

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