Charge Pump

A charge pump is a circuit that generates a DC voltage higher than its own supply rail using nothing but switches and capacitors — no inductor, no external magnetic component, no second power supply — by repeatedly shuttling small packets of charge through a chain of capacitors clocked out of phase with each other, each stage adding roughly one more clock swing's worth of voltage on top of the last.

The classic Dickson charge pump topology makes the mechanism almost mechanically simple: a chain of capacitors, each one connected to the next through a switch, with alternating clock phases driving alternating capacitors. When a capacitor's switch opens during one clock phase, that capacitor's bottom plate gets pulled up by the clock signal while its stored charge stays put, which pushes its top-plate voltage up by roughly the clock's own swing; a switch to the next stage then passes that elevated charge forward before the clock phases reverse and the process repeats on the next capacitor in the chain. Each stage contributes its own incremental voltage boost, so an N-stage pump produces an output roughly N times the clock swing above the input — though real circuits lose some of that ideal gain to switch resistance, parasitic capacitance, and whatever load current the output actually has to supply.

This is exactly how NAND and NOR flash memory generate the programming and erase voltages their own supply rail cannot provide directly. A typical chip's external supply sits well below the ten-to-twenty-volt range flash programming and erase operations actually require at the memory array, and routing a separate, higher external supply onto the board solely for this purpose would be both wasteful and impractical — an on-chip charge pump instead steps the existing supply up internally, generating exactly the elevated voltage incremental step pulse programming needs to push charge onto a floating gate, with no additional pin or external component required. DRAM uses the identical trick for its own word-line boost voltage, typically called VPP, which has to sit above the core supply specifically so an access transistor can pass a full logic-one level into a storage capacitor without losing a threshold voltage's worth of charge along the way.

The tradeoff against an inductor-based boost converter is a direct current-capability-for-integration swap, not a universal winner. A charge pump's entire energy storage and transfer mechanism lives in capacitors small enough to fit directly on the same die as the rest of the chip, requiring zero external components — but a capacitor's charge-transfer efficiency and maximum deliverable current both degrade as load current rises, since every charge transfer through a finite switch resistance dissipates real power, and that loss compounds across however many stages the design needs. An inductor-based boost converter, built from the same power-stage topology this series has already covered for point-of-load voltage regulation, stores energy in a magnetic field rather than electric charge and can deliver substantially more current at higher efficiency — but it needs a real, discrete inductor that cannot be integrated onto the die the way a charge pump's capacitors can.

This is precisely why memory programming voltages pick the charge pump deliberately rather than defaulting to whichever topology is generally more efficient. A flash or DRAM boost rail typically only needs to source leakage current and whatever modest current the programming operation itself draws — nowhere near the current an inductive converter is built to deliver efficiently — so the charge pump's comparatively poor current capability is simply never exercised, while its complete on-chip integration is worth far more than the efficiency an inductor would buy. A design that instead needed to deliver real load current at a boosted voltage, the way a motor driver or an LED backlight supply might, would make the opposite choice, accepting an external inductor's board-space cost for the current capability a charge pump cannot match.

Charge pump efficiency and output impedance both depend directly on the same clock frequency and stage count that set its voltage gain, which creates a real design tension rather than a free choice of more stages for more voltage. Running the clock faster moves more charge packets per second through the same capacitors, raising achievable output current for a given capacitor size, but faster switching also means more frequent charge-transfer loss events, pulling efficiency down the same way switching loss trades against conduction loss in any switched power circuit. More stages buy more voltage headroom but each additional stage adds its own switch resistance and charge-transfer loss in series with every stage before it, which is why practical flash and DRAM charge pumps are sized to the minimum stage count that reaches the required voltage rather than over-provisioned for margin that costs real efficiency to carry.

A charge pump is the specific answer to a narrow but recurring problem: generating a voltage higher than the supply rail, on-chip, with low current demand, no external components, and no second power source. Flash memory programming and DRAM word-line boost both need exactly this combination of requirements, which is why the charge pump — rather than the more generally efficient inductive converter — is the default topology wherever a chip has to manufacture its own elevated voltage internally rather than ask the board for one.