chiplet architecture
**Chiplet Architecture** is a **modular chip design approach that decomposes a large monolithic die into multiple smaller dies (chiplets) connected through advanced packaging** — improving manufacturing yield, enabling mix-and-match of different process nodes, and creating scalable product families from reusable building blocks, as demonstrated by AMD's Ryzen/EPYC processors, Intel's Ponte Vecchio, and NVIDIA's Blackwell GPU.
**What Is Chiplet Architecture?**
- **Definition**: A design methodology where a system-on-chip (SoC) is partitioned into multiple smaller dies (chiplets), each fabricated independently and then assembled into a single package using 2.5D interposers, silicon bridges, or advanced fan-out packaging to create a system that functions as a unified chip.
- **Monolithic vs. Chiplet**: A monolithic 800 mm² die has ~30% yield on advanced nodes — splitting it into four 200 mm² chiplets improves per-chiplet yield to ~70%, and using known-good-die (KGD) testing before assembly achieves ~50% package yield, dramatically reducing effective cost.
- **Functional Partitioning**: Chiplets are typically partitioned by function — compute chiplets (CPU/GPU cores) on the most advanced node, I/O chiplets (SerDes, memory controllers) on a mature cost-effective node, and memory (HBM) on DRAM process.
- **Product Scalability**: The same chiplet building blocks create an entire product family — AMD uses 1, 2, 4, or 8 compute chiplets (CCDs) with a common I/O die (IOD) to span from desktop Ryzen to server EPYC processors.
**Why Chiplet Architecture Matters**
- **Yield Economics**: The cost advantage of chiplets grows with die size and node advancement — at 3nm, a chiplet approach can reduce effective die cost by 30-60% compared to a monolithic design of equivalent functionality.
- **Design Reuse**: A proven I/O chiplet can be reused across 3-5 product generations and multiple product lines — amortizing the $500M-1B design cost over many more units than a single monolithic design.
- **Technology Mixing**: Each chiplet uses its optimal process — compute on 3nm for density, I/O on 6nm for analog performance, memory on DRAM process for capacity — impossible with a monolithic approach.
- **Time-to-Market**: Designing a new compute chiplet while reusing proven I/O and memory chiplets reduces design cycle from 3-4 years to 1.5-2 years for derivative products.
**Chiplet Architecture Examples**
- **AMD Ryzen/EPYC**: Pioneered the chiplet approach — 8-core compute chiplets (CCD) on TSMC 5nm connected to an I/O die (IOD) on 6nm. Desktop: 1-2 CCDs. Server: up to 12 CCDs (96 cores).
- **Intel Ponte Vecchio**: 47 chiplets (tiles) across 5 process technologies — compute tiles on Intel 7, base tiles on TSMC N5, Xe Link tiles on TSMC N7, EMIB bridges, and Foveros 3D stacking.
- **NVIDIA Blackwell (B200)**: Two GPU compute dies connected by a 10 TB/s NVLink-C2C chip-to-chip interconnect on TSMC 4nm — the first NVIDIA GPU to use a multi-die architecture.
- **Apple M1 Ultra**: Two M1 Max dies connected by UltraFusion (TSMC LSI bridge) with 2.5 TB/s bandwidth — demonstrating chiplet scaling for consumer products.
| Product | Chiplets | Compute Node | I/O Node | Interconnect | Total Transistors |
|---------|---------|-------------|---------|-------------|------------------|
| AMD EPYC 9654 | 12 CCD + 1 IOD | TSMC 5nm | TSMC 6nm | Infinity Fabric | ~90B |
| Intel Ponte Vecchio | 47 tiles | Intel 7 | TSMC N5/N7 | EMIB + Foveros | 100B+ |
| NVIDIA B200 | 2 GPU dies | TSMC 4nm | Integrated | NVLink-C2C | 208B |
| Apple M1 Ultra | 2× M1 Max | TSMC 5nm | Integrated | UltraFusion | 114B |
| AMD MI300X | 8 XCD + 4 IOD | TSMC 5nm | TSMC 6nm | IF + 2.5D | 153B |
**Chiplet architecture is the modular design revolution transforming semiconductor product development** — decomposing monolithic dies into reusable, independently optimized building blocks that improve yield, reduce cost, accelerate time-to-market, and enable scalable product families, establishing the dominant design paradigm for high-performance processors and AI accelerators.