chiplet known good die

**Known Good Die (KGD) Testing** is the **rigorous probe-testing methodology applied to bare, unpackaged semiconductor dies while still on the wafer, guaranteeing their full electrical functionality and reliability before integrating them into expensive multi-die heterogeneous packages or 3D-IC stacks**. Historically, standard chips were only partially tested on the wafer to weed out gross manufacturing defects (opens/shorts). The expensive, comprehensive functional testing (at full speed and extreme temperatures) was reserved for the final packaged product. However, the rise of advanced packaging (Chiplets, HBM, CoWoS, FO-WLP) completely broke this economic model. **The Multi-Die Yield Problem**: If you assemble 10 chiplets onto a massive $500 silicon interposer package, and every chiplet has a 95% yield (95% chance of working), the final package yield is 0.95^10 = **59.8%**. You will throw away 40% of these immensely expensive assembled packages because a single $10 die failed. To achieve 95% final package yield with 10 chiplets, you need every individual chiplet to be **99.5%** guaranteed to work before assembly. This demands True KGD. **KGD Test Challenges**: - **Micro-bump Contacting**: Modern chiplets use tens of thousands of microscopic copper bumps (like 40μm pitch). Building a mechanical probe card with 10,000 microscopic needles that can physically touch these bumps without destroying them, while delivering hundreds of amps of power for testing, is a staggering electromechanical challenge. - **Thermal Dissipation**: Bare silicon has no heat spreader. Running a high-performance bare die at full speed during a wafer probe test generates immense localized heat that can instantly crack the wafer or melt the probe tips. - **Speed Limits**: Long mechanical probe needles act as microscopic antennas and inductors, destroying the signal integrity of high-speed SerDes (like PCIe Gen5) or HBM interfaces. Often, full-speed testing is physically impossible on bare silicon. **Design for Test (DFT)**: To achieve KGD, designers heavily instrument the chiplet with Built-In Self-Test (BIST) circuits, internal loopback structures, and massive JTAG scan chains. The chip tests itself internally, minimizing the external high-speed signals required from the probe card. KGD is the fundamental economic enabler of the Chiplet era — if the bare silicon is not guaranteed good before bonding, the advanced packaging revolution collapses under the cost of compounded yield loss.