semiconductor test wafer sort

**Wafer Sort (Probe Testing)** is the **pre-packaging electrical test performed by contacting every die on the wafer with precision probe needles — executing functional tests, scan-chain structural tests, and parametric measurements to identify Known Good Die (KGD) before committing to expensive packaging, where test costs represent 5-15% of total manufacturing cost and achieving adequate test coverage and fault detection directly determines the quality shipped to customers**. **Why Test Before Packaging** Packaging a single advanced die costs $5-50+ (advanced substrates, flip-chip assembly, underfill, lid attach). Testing at wafer level costs $0.10-1.00 per die. Identifying and discarding defective dies before packaging saves millions of dollars annually. For 2.5D/3D chiplet architectures, Known Good Die (KGD) qualification is essential — bonding a defective die into a multi-die package wastes all the good dies in that package. **Probe Card Technology** - **Cantilever Probes**: Traditional bent metal wires. Low cost, suitable for peripheral pad designs up to a few hundred I/O. Cannot handle area-array (bumped) dies. - **MEMS Probes**: Photolithographically fabricated micro-spring contacts. Handle area-array bumps at 40-100 μm pitch with thousands of simultaneous contacts. Cost: $50K-500K per probe card. Lifetime: 1-5M touchdowns. - **Vertical Probes**: Spring-loaded pins in a guide plate. Fine pitch, high parallelism. Dominant technology for advanced logic and HBM testing. **Test Content** - **Continuity and Leakage**: Verify all I/O pads are connected and no shorts exist between adjacent signals. The first and fastest test, catching gross fabrication defects. - **Scan Chain Test (ATPG)**: Shift test patterns through scan chains that access every flip-flop in the design. Automatic Test Pattern Generation (ATPG) creates vectors that detect >99% of stuck-at faults and >95% of transition faults. This is the primary structural test, catching transistor-level manufacturing defects. - **BIST (Built-In Self Test)**: On-chip test engines exercise memory arrays (MBIST), logic blocks (LBIST), and I/O interfaces (SerDes BIST) without external pattern generation. Essential for testing embedded memories (SRAM, register files) that have too many cells for external test. - **Speed Binning**: Functional tests at different frequencies identify the maximum operating speed of each die. Dies are sorted into speed bins (e.g., 3.0 GHz, 3.2 GHz, 3.4 GHz) for different product SKUs. **Multi-Die Testing** Modern probers can test multiple dies simultaneously (4, 8, or 16 at a time) to improve throughput. The probe card contacts multiple die sites, and the tester runs tests in parallel. For high-volume products, multi-site testing reduces per-die test cost by 3-8x. Wafer Sort is **the quality gate where silicon meets accountability** — every die is electrically interrogated before it earns the right to be packaged, ensuring that only functional, speed-qualified dies proceed to the expensive final stages of semiconductor manufacturing.