CMOS-Bonded-Array

Separate fabrication followed by direct integration. CMOS bonded to array refers here to Kioxia’s CMOS directly Bonded to Array, or CBA, technology for 3D NAND flash. The memory-cell array and peripheral CMOS circuits are fabricated on separate wafers under conditions suited to each structure, then connected using direct bonding. This changes the integration sequence rather than changing the fundamental distinction between nonvolatile NAND storage and volatile DRAM.

Independent thermal budgets are valuable. Building a tall NAND array involves processing conditions that can constrain nearby peripheral transistors. Separate fabrication allows the array and CMOS processes to be optimized with greater independence before they are joined. The eventual combined device still needs reliable electrical connections and compatible wafer geometry. Separation creates process freedom, but it also adds bonding preparation, alignment, inspection, and yield-management requirements.

Copper bonding creates the electrical interface. Kioxia describes CBA as using copper direct bonding. Dense connections link the separately manufactured portions so that peripheral circuitry can address and operate the memory array. Surface preparation, planarity, cleanliness, and alignment are critical because defects at the interface can disable otherwise useful circuitry. The quality of this interface is part of the complete memory manufacturing flow, rather than a packaging detail that can be evaluated in isolation.

BiCS FLASH generation 8 is a documented example. Kioxia identifies CBA as a technology applied to its eighth-generation BiCS FLASH. Its published material describes a 218-layer array for that generation. This is a specific implementation, not a definition requiring all CBA devices to have 218 layers. Layer count, interface rate, cell organization, and peripheral technology remain separate parameters that can evolve across later products.

Evaluate the combined manufacturing economics. Potential benefits include independent optimization of array and logic, efficient area use, and improved operating characteristics. Costs include additional wafer processing, bonding equipment, interface defects, and the loss of value when joined components fail. A useful comparison states bit density, throughput, power, reliability, and yield for the finished device. CBA should therefore be understood as an integration architecture, not merely as a larger NAND layer count.

Sources and further reading. [Kioxia CBA technology explanation](https://www.kioxia.com/en-jp/rd/technology/cba.html); [Kioxia generation 8 technology note](https://europe.kioxia.com/content/dam/kioxia/en-europe/business/memory/asset/KIE_NL_20250122-1_EN.pdf).

Read CMOS bonded to array as a wafer-integration approach that joins separately optimized NAND arrays and peripheral CMOS.