CMOS Crossover 1980 Size Decoupling Capacitance Switching Noise Budget

# Size a Local Reservoir of Charge So the Grid Never Has to Answer Instantly

## 1. Separate What the Grid Can Supply Quickly From What a Transition Demands Instantly

Step 4 showed that the disturbance $V_{dd}-L\,di/dt-iR$ grows with how many gates switch together, and that the parasitic inductance $L$ is a property of the package and die's physical power distribution network — something not freely reducible once a package is chosen. What *can* be engineered directly is the source the switching current actually draws from in the first few hundred picoseconds of a transition, before the inductive path even has time to respond. That source is decoupling capacitance: capacitors placed physically close to the switching gates, charged and ready, that supply the transient current locally so the slower, inductance-limited path from the package pins never has to answer the full demand instantly.

The sizing logic follows directly from the noise budget a design is willing to tolerate. If $N$ gates switch simultaneously, each drawing the charge packet $C_LV_{dd}$ Step 4 derived, and the design can tolerate a supply droop of at most $\Delta V_{max}$, the decoupling capacitor must hold enough charge that supplying the full transient current itself does not let its own voltage sag past that budget:

$$C_{decap}\ge\frac{N\,C_L\,V_{dd}}{\Delta V_{max}}$$

This is a direct, first-principles sizing rule, not a rule of thumb: it says exactly how much local charge reservoir a given switching activity and noise tolerance require, and it scales linearly with $N$ — the same simultaneous-switching count that made Step 4's problem worse as density rose is precisely the term that makes this step's required capacitance grow.

A Local Reservoir Answers the Instant; the Grid Answers the Average decoupling capacitance supplies the transient so the inductance-limited path never has to PACKAGE PINS slow, inductance-limited DECOUPLING CAP local, fast, pre-charged SWITCHING GATES draw i(t) in <τ C_decap ≥ N·C_L·V_dd / ΔV_max N = gates switching together, ΔV_max = tolerable supply droop grows directly with the same N that made Step 4's disturbance worse this capacitance occupies die area too a direct silicon cost for the noise budget — Section 2

## 2. Place the Decoupling Capacitor Physically, Where Distance Itself Becomes a Parasitic

A decoupling capacitor's usefulness is not determined by its capacitance value alone. The wire connecting it to the switching gate carries its own parasitic inductance $L_{wire}$, proportional to the physical distance between the two, and that inductance reintroduces exactly the problem the capacitor was placed to solve:

$$V_{supply,local}=V_{dd}-L_{wire}\frac{di}{dt}-\frac{1}{C_{decap}}\int i\,dt$$

A decoupling capacitor placed too far from its switching gates recovers none of its intended benefit, because $L_{wire}\,di/dt$ dominates the same way the package-level inductance did in Step 4. This is why decoupling capacitance in a dense CMOS design is distributed throughout the die rather than concentrated at a few large reservoirs near the power pins — on-chip decoupling capacitors, built from thin-oxide MOS structures or dedicated metal-insulator-metal plates, sit directly adjacent to the dense logic blocks most likely to switch simultaneously, trading area locally for a wire short enough that $L_{wire}$ stays small.

Distance Between Cap and Gate Reintroduces the Same Inductance Real Diagram — a far decoupling cap and a near decoupling cap buy very different noise margins FAR DECOUPLING CAP long wire → large L_wire benefit mostly lost to L_wire·di/dt NEAR DECOUPLING CAP short wire → small L_wire most of C_decap's benefit is preserved V_supply,local = V_dd − L_wire·di/dt − (1/C_decap)∫i dt placement, not just capacitance value, determines how much Step 4's disturbance actually shrinks decoupling must be distributed throughout dense logic, not centralized area spent locally, everywhere density is highest the real cost of answering Step 4's problem at this density

## 3. Close the Noise-and-Cost Thread This Series Has Carried Since Step 2

This step completes a specific accounting thread running through Steps 2 through 5: every structural fix this series has introduced to make CMOS work at 1980s density — guard rings against latchup, now decoupling capacitance against switching noise — has had both a governing equation and a direct silicon-area cost, following the same discipline the project applied to DRAM's trench-versus-stacked tradeoff and HMOS's clock-speed payoff. Decoupling capacitance is not a free fix layered on top of the crossover's power savings; it is area that must be budgeted alongside the guard-ring area from Step 3, both paid specifically because density made CMOS's latent properties — the parasitic bipolar pair, the sharp switching pulse — consequential rather than negligible.

What makes this particular cost distinct from Step 3's is where it must be spent: guard-ring area scales with device perimeter and must surround every well boundary, while decoupling capacitance must be distributed near every block of logic dense enough to switch many gates on one clock edge, which in practice means it follows activity density rather than well count. A designer budgeting silicon at this point in the project's CMOS lineage is now accounting for two independent area taxes, each driven by a different consequence of the same underlying density increase. The next step turns from these per-structure costs to the system-level question this series opened in Step 1: with latchup managed and switching noise budgeted, what does the complete power-delay-density comparison between 1980s CMOS and the HMOS generation it replaced actually look like, measured the same way 1978's own Step 9 measured NMOS against the generation it displaced.

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