CMOS Crossover 1980 Simultaneous Switching Noise Power Distribution

# Confront the Current Spike: Why CMOS's Clean Power Term Creates a Dirty Power Grid

## 1. Contrast the Current Waveform CMOS Actually Draws Against the One NMOS Always Drew

Step 1 of this series established that CMOS eliminates $P_{static}=I_{DD}V_{dd}$ by construction — in steady state, one transistor of every complementary pair is off, and no continuous current path exists. This is true, and it is the entire reason the crossover happened. But it describes the time-*averaged* current, not the instantaneous current, and the instantaneous waveform CMOS draws is qualitatively different from anything the NMOS lineage this project has traced since 1967 ever produced.

A ratioed NMOS inverter draws a roughly steady current whenever its output sits low — a smooth, continuous load on the power supply, exactly the $I_{DD}$ term Step 1 identified as wasteful but also, incidentally, easy on the power distribution network, because a steady current produces no sudden demand. A CMOS gate draws current only while *switching*, and it draws that current as a sharp pulse: both transistors conduct briefly during the transition, and the output capacitance charges or discharges through a current spike lasting only the transition time $\tau$:

$$i(t)\approx C_L\frac{dV_{out}}{dt},\qquad \int_0^{\tau} i(t)\,dt = C_LV_{dd}$$

The same charge that used to flow as a gentle, continuous trickle under NMOS now flows as a brief, sharp impulse under CMOS. Averaged over time this is exactly the $P_{dynamic}$ savings the crossover was built on. Examined at the timescale of a single clock edge, it is a current waveform the power distribution network was never designed to carry.

Same Average Charge, Very Different Current Shape NMOS drew current as a steady trickle; CMOS draws the same charge as a sharp pulse NMOS: STEADY I_DD continuous current while output LOW gentle, predictable load on supply CMOS: PULSED i(t) sharp spike only during transition τ same ∫i dt = C_L·V_dd, concentrated in time ∫i(t)dt = C_L·V_dd IN BOTH CASES P_dynamic's average savings are real — but the instantaneous demand just got sharper a sharp pulse through a real power grid meets parasitic inductance it never had to fight before — Section 2

## 2. Show How Many Simultaneous Pulses Become a Voltage Drop the Chip Cannot Ignore

A power distribution network — the bond wires, package leads, and on-chip metal supplying $V_{dd}$ and ground to every gate — is not an ideal zero-impedance source. It carries parasitic series inductance $L$ and resistance $R$ accumulated across package and die. The voltage actually delivered at a gate during a current transient is:

$$V_{supply,actual}=V_{dd}-L\frac{di}{dt}-iR$$

For NMOS's steady $I_{DD}$, $di/dt\approx 0$ almost always, so the inductive term stays negligible and only the comparatively small resistive drop matters. For CMOS's sharp switching pulse, $di/dt$ is large by construction — that sharpness is exactly what made the average power savings real — and when a large number of gates switch at the same clock edge, their individual pulses sum into an aggregate $di/dt$ large enough to pull $V_{dd}$ down and ground up by a significant fraction of a volt for the duration of the transient. This is simultaneous switching noise, commonly observed as ground bounce: a supply disturbance that did not exist as a meaningful design concern in the NMOS lineage, because no prior series' device ever asked the power grid to source or sink current that fast, that many times per clock cycle, across that many gates simultaneously.

Many Simultaneous Pulses Sum Into a Supply Disturbance Real Diagram — parasitic L and R turn a clean switching edge into a dirty supply rail SINGLE GATE SWITCHING one pulse, small di/dt contribution L·di/dt term stays negligible alone supply voltage holds steady no design concern at low density MANY GATES, SAME EDGE thousands of pulses align in time aggregate di/dt grows with density V_dd droops, ground bounces 1980s density makes this unavoidable V_supply,actual = V_dd − L·di/dt − i·R a disturbance that scales with how many gates switch together, not with any single transistor's size a false logic transition can be triggered if the disturbance is large enough decoupling capacitance and grid design absorb it another cost the crossover's power savings must still budget for

## 3. Place This Alongside the Project's Other Density-Revealed Costs

This step belongs with Steps 2 and 3 as a third instance of the same pattern this series keeps surfacing: a property of CMOS that was present and harmless at 1963's density becomes a genuine engineering problem only once density and switching activity climb far enough. Just as the parasitic bipolar pair in Step 2 was always latent and only became dangerous as well spacing shrank, the sharp current pulse described here was always the mechanism behind CMOS's power savings — it did not newly appear in 1980. What is new is the number of gates whose pulses now align closely enough in time, on one die, to sum into a disturbance the power grid must be explicitly engineered to absorb.

This also connects directly to a concern this project raised from the NMOS side: the 1978 HMOS series' Step 5 confronted interconnect RC delay becoming comparable to gate delay as switching speed increased. That step was about signal propagation through resistive, capacitive wiring. This step is about power delivery through inductive, resistive wiring — the same physical power-distribution network, stressed by a different mechanism. Both findings point to the same underlying fact: as both the NMOS and CMOS lineages this project has traced increased density and speed, the wiring connecting devices together — not the devices themselves — became an independent design problem in its own right. The next step follows that thread specifically for CMOS: how decoupling capacitance and power-grid design are sized to keep simultaneous switching noise within a budget the logic can tolerate.

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