CMP Dishing Erosion Naming

Dishing and erosion are named by where on the chip the over-polish happens, a wide single feature versus a densely packed array, and that location is the entire difference between two defects that both come from the same chemical-mechanical polishing step overshooting its target. After a damascene copper fill, CMP is supposed to stop exactly at the dielectric surface, removing only the excess copper above it; dishing names a recess that forms inside one wide copper feature, while erosion names a recess that forms across a cluster of closely spaced thin dielectric lines between copper features. Same tool, same slurry, two different names because the pad presses down differently depending on what pattern is underneath it.

A few things explain why these two overshoot defects earned separate names instead of a single "overpolish" label:

Dishing is named for the bowl-shaped recess it leaves in one feature, and the mechanism is pad compliance over a soft, wide area. A polishing pad is not perfectly rigid; across a wide copper pad (soft relative to the surrounding harder dielectric), the pad can flex slightly downward and keep removing copper even after the surrounding dielectric has reached its target height, carving a shallow dish into the feature's center. Wider features dish more than narrow ones for exactly this reason, which is why dishing is reported as a function of feature width, not as a single chip-wide number.

Erosion is named for the way it wears down a dense region as a whole rather than a single feature, and the mechanism is pattern-density-dependent removal rate. In an area packed with many thin copper lines separated by thin dielectric lines, the polish removes material from the whole dense cluster faster than it removes material from an isolated wide dielectric field nearby, so both the copper and the dielectric in that dense region end up lower than their counterparts elsewhere on the chip — the entire local neighborhood erodes together, which is the pattern-density signature that distinguishes it from dishing's single-feature signature.

Pattern design rules exist largely to keep both of these named defects within budget, which is why the naming matters to a layout engineer, not just a process engineer. Maximum copper feature width and minimum dielectric-line density in a layer are frequently set by how much dishing or erosion the CMP process is known to produce at a given geometry, meaning the names show up directly as design-rule-manual entries rather than staying confined to a process-engineering vocabulary.

Siblings worth distinguishing: this entry covers the two named overshoot defects from the polishing step itself; it does not cover damascene naming (the inlay process that creates the copper feature CMP then polishes, covered elsewhere) or CD bias naming (a lithography and etch pattern-density effect on linewidth, a different step and a different named mechanism than this polish-step overshoot).

Read "dishing" and "erosion" as location labels for the same overshoot mechanism rather than as two unrelated defects: dishing happens inside one wide feature because the pad is soft enough to flex over it, erosion happens across a dense cluster because the whole neighborhood polishes away faster than the sparse field around it, and both numbers end up constraining the same design rule — how wide a single feature, or how dense a line array, is allowed to be before CMP starts eating into the copper or dielectric that's supposed to stay flush.