cobalt fill process
**Cobalt Fill Process** is the **CVD and electroless-plating technique for filling contact holes and vias with cobalt metal as an alternative to tungsten** — offering lower resistivity for narrow features (< 15 nm diameter), eliminating the thick TiN barrier requirement, and enabling lower contact resistance at advanced nodes where the barrier metal consumes an unacceptable fraction of the available plug volume.
**Why Cobalt Instead of Tungsten?**
| Property | Tungsten (W) | Cobalt (Co) |
|----------|-------------|------------|
| Bulk resistivity | 5.3 μΩ·cm | 6.2 μΩ·cm |
| Barrier required | TiN (3-5 nm) | None or very thin |
| Effective resistivity (< 15 nm plug) | High (barrier eats volume) | Lower (more conductor) |
| Fill method | CVD (WF6/H2) | CVD + reflow or electroless |
| Grain structure | Columnar, resistive boundaries | Reflowable, large grains |
- At 15 nm contact diameter: 5 nm TiN barrier leaves only 5 nm of W → most of the plug is barrier.
- Cobalt can be deposited with minimal or no barrier → more metal, lower resistance.
**Cobalt CVD Process**
1. **Barrier (optional)**: Ultra-thin TiN or TaN (~1-2 nm) — if needed for adhesion.
2. **Co CVD nucleation**: Cobalt precursor (Co2(CO)8 or similar) + H2 at 150-200°C.
3. **Co CVD fill**: Continue deposition to fill contact/via.
4. **Anneal/Reflow**: 300-400°C causes cobalt grain growth and void elimination.
5. **CMP**: Polish back excess cobalt.
**Cobalt Reflow Advantage**
- Unlike tungsten, cobalt can be **reflowed** at moderate temperature.
- Reflow fills small voids and seams that form during initial CVD fill.
- Result: Void-free fill even in features with re-entrant profiles.
- This is cobalt's key differentiator over tungsten for the smallest features.
**Where Cobalt Is Used**
- **Intel 10nm (Intel 7)**: Introduced cobalt for M0/M1 (thinnest interconnect layers).
- **Contact level**: Some foundries use Co for source/drain contacts (replacing W).
- **Via0**: The via connecting contact to M1 — critical for resistance.
- **Cobalt cap (CoWP)**: Selective cobalt deposition on Cu lines — improves EM resistance.
**Challenges**
- **Oxidation**: Cobalt oxidizes readily — must maintain reducing atmosphere during processing.
- **Precursor cost**: Cobalt CVD precursors more expensive than WF6.
- **Selectivity**: Achieving selective cobalt deposition (only inside features, not on field) is difficult.
- **Reliability**: Cobalt EM behavior different from W — characterization needed per integration scheme.
**Beyond Cobalt: Ruthenium**
- At < 10 nm dimensions, even cobalt resistivity becomes limiting.
- Ruthenium (Ru): Lower electron scattering at nanoscale → potentially lower effective resistivity.
- Ru does not need a barrier at all — deposited directly on dielectric.
- Active R&D at 2nm/1.4nm nodes.
The cobalt fill process is **a key materials innovation for the most advanced semiconductor nodes** — by solving the barrier-thickness overhead problem that plagued tungsten contacts at sub-15nm dimensions, cobalt enables the lower contact resistance essential for maintaining transistor drive current at each new generation.