contact resistivity scaling cobalt

**Contact Resistivity Scaling with Cobalt Liner** is **the metallization strategy that replaces conventional titanium-based liner/barrier schemes with cobalt-based contact metallurgy to reduce contact resistance below 1×10⁻⁹ Ω·cm² at the metal-semiconductor interface, addressing the dominant parasitic resistance bottleneck in sub-5 nm transistor performance**. **Contact Resistance Challenge at Advanced Nodes:** - **Parasitic Dominance**: at sub-5 nm nodes, contact resistance accounts for 40-60% of total device on-resistance (Ron), up from <20% at the 28 nm node - **Scaling Physics**: contact area shrinks quadratically with pitch scaling while interface resistance remains relatively constant, causing Rc to increase as ~1/A_contact - **Contact Dimensions**: middle-of-line (MOL) contact dimensions of 10-18 nm diameter at N3/N2 nodes with aspect ratios of 5:1 to 8:1 - **Resistance Budget**: total S/D contact resistance target of 50-100 Ω per contact at N3, requiring specific contact resistivity (ρc) below 1×10⁻⁹ Ω·cm² **Cobalt Liner Integration:** - **Liner Function**: 1-3 nm cobalt liner deposited by CVD or ALD between TiN barrier and tungsten fill plug—provides adhesion, nucleation, and fill improvement - **CVD Cobalt**: deposited using Co₂(CO)₈ or CCTBA (cyclopentadienyl cobalt bis-carbonyl) precursors at 150-250°C—provides superior step coverage (>95%) in high-aspect-ratio contacts - **Reflow Capability**: cobalt undergoes solid-state grain growth and reflow at 300-400°C anneal, filling seams and voids that plague conventional TiN/W contacts - **Resistivity Advantage**: bulk cobalt resistivity (6.2 µΩ·cm) is lower than TiN (13-25 µΩ·cm), reducing liner contribution to total contact resistance by 30-40% **Metal-Semiconductor Interface Engineering:** - **Silicide Formation**: Ti-based silicide (TiSi₂) at NMOS contacts with Schottky barrier height (SBH) of 0.5-0.6 eV; NiSi for legacy nodes at 0.65 eV SBH - **Cobalt Silicide Contact**: CoSi₂ formation at 600-700°C provides thermally stable low-resistance contact with SBH of 0.64 eV on n-Si—requires precise temperature control to avoid CoSi agglomeration - **Dipole Engineering**: inserting 0.2-0.5 nm TiO₂ or ZnO interlayer between metal and Si creates interface dipole reducing effective SBH by 0.1-0.3 eV - **Fermi-Level Depinning**: MIS (metal-insulator-semiconductor) contact structures with ultra-thin dielectrics (<1 nm) partially depin the Fermi level, enabling SBH below 0.3 eV **Contact Metallization Process Flow:** - **Contact Etch**: high-aspect-ratio contact holes etched through SiN/SiO₂ ILD using C₄F₈/Ar/O₂ chemistry with >30:1 selectivity to etch stop layers - **Pre-Clean**: siconi (NH₃/NF₃ remote plasma) or Ar sputter clean removes native oxide from S/D epi surface without damaging ultra-shallow junctions - **Ti/TiN Barrier**: 1-2 nm Ti + 1-2 nm TiN deposited by PVD or ALD—Ti reacts with Si to form TiSi₂ during subsequent anneal - **Cobalt Liner Deposition**: 2-3 nm CVD Co provides nucleation layer for tungsten fill and improves electromigration resistance - **Tungsten Fill**: low-fluorine CVD W using B₂H₆ nucleation + WF₆/H₂ bulk fill—cobalt liner improves W grain size and reduces resistivity by 15-20% **Beyond Cobalt—Ruthenium and Molybdenum Contacts:** - **Ruthenium Contacts**: Ru offers lower electron mean free path scattering at scaled dimensions, maintaining bulk-like resistivity (7.1 µΩ·cm) at widths below 15 nm - **Molybdenum Fill**: Mo (bulk ρ = 5.2 µΩ·cm) emerging as tungsten replacement for contact fill at N2 and beyond due to superior resistivity scaling and lower deposition temperature **Contact resistivity scaling with cobalt liner technology is a critical enabler for sub-3 nm transistor performance, where every ohm of parasitic resistance reduction translates directly to higher drive current and lower operating voltage, making contact metallurgy innovation as important as transistor architecture advancement for continued Moore's Law scaling.**