cobalt liner ald

Copper interconnect scaling ran into a hard physical wall once trench and via dimensions shrank past the point where a sputtered PVD copper seed layer could still coat a sidewall continuously: below roughly 20 nm, PVD line-of-sight deposition simply cannot reach the bottom and lower sidewall of a high-aspect-ratio feature without leaving gaps, and a discontinuous seed means a void in the finished copper fill. Atomic layer deposition of a thin cobalt liner, paired with a ruthenium seed that copper can be electroplated directly onto, replaced that PVD seed step specifically because ALD's self-limiting, conformal growth mechanism does not care how deep or narrow the feature is, coating the via bottom as evenly as the field region above it. That shift, from a line-of-sight physical deposition to a chemically self-limiting one, is arguably the single most consequential process change in the back-end-of-line stack over the last several technology generations, since without it the entire dual-damascene copper scheme would have stalled at whatever pitch PVD seed could still reach. **The cobalt liner is grown by ALD in a self-limiting cycle that deposits a highly conformal film across sidewall, corner, and via bottom alike, typically building up to a total thickness of 1 nm to 3 nm depending on the target node and the fill margin required.** Because each ALD cycle adds a fixed, sub-nanometer increment, roughly 0.05 nm to 0.15 nm per cycle depending on precursor chemistry and surface temperature, liner thickness is set directly by cycle count rather than by a timed deposition, giving repeatable control that a timed PVD or CVD process struggles to match at these dimensions. Deposition temperature for a typical Co ALD process runs in the 150 °C to 250 °C range, chosen to keep the precursor chemistry self-limiting rather than drifting into a CVD-like, non-conformal growth regime. Precursor pulse and purge timing is commonly held in the 1 s to 3 s range per half-cycle, since an under-purged cycle risks parasitic CVD growth that degrades the very conformality ALD exists to provide. **Ruthenium seed layers replaced PVD copper seed at the tightest pitches because Ru, unlike bare cobalt or bare barrier material, supports direct copper electroplating without a separate PVD seed step, closing the gap left when PVD seed coverage became unreliable below about 20 nm.** A Ru seed film in the 1 nm to 2 nm range is typically sufficient to nucleate continuous copper electroplating across the full via and trench surface, and because Ru is deposited by the same class of conformal ALD or CVD process as the cobalt liner beneath it, the combined liner-plus-seed stack maintains its conformality all the way to the via bottom. Adhesion of copper to a Ru seed is generally stronger than adhesion to bare cobalt, which is one of the practical reasons the two layers are used together rather than relying on cobalt alone to both block diffusion and seed the fill. Seed continuity is checked before electroplating begins, since a seed layer with even a few % coverage gaps at the via bottom reliably produces a fill void at that location. Ru seed deposition rate is typically held near 0.03 nm to 0.08 nm per cycle, slower than the cobalt liner growth rate beneath it, and total Ru ALD cycle count for a 1.5 nm target commonly falls in the range of 20 to 40 cycles depending on precursor and substrate temperature. **Bottom-up copper fill depends on more than just seed continuity: the fill mechanism itself has to be biased to nucleate and grow preferentially from the via bottom upward, rather than pinching off at the top of a narrow opening before the bottom has filled.** Plating-bath additives, accelerators, suppressors, and levelers, are tuned so that copper growth rate is highest at the via base and lowest at the field surface, a chemistry-driven bias that depends on the additives reaching a uniformly seeded surface in the first place. A liner and seed stack with even minor thickness nonuniformity, say a 20% to 30% thinning near the via bottom relative to the field, can shift the effective plating bias enough to produce a marginal void that would not appear on a thicker, more forgiving seed stack. ALD nucleation density on the underlying barrier surface is itself a process variable, since a low initial nucleation density can leave the first several ALD cycles non-continuous even though steady-state growth eventually becomes conformal. **The liner's own resistance contribution becomes a bigger fraction of total via resistance as pitch shrinks, since a fixed-thickness liner occupies a growing percentage of a shrinking via's cross-sectional area.** At a trench width of roughly 40 nm, a 1 nm to 2 nm liner-plus-seed stack contributes a relatively small share of total line resistance, but at trench widths below 15 nm that same absolute liner thickness can account for a resistance contribution rising several times over, since the liner no longer scales down proportionally with the shrinking copper cross-section. This is the central trade-off in liner scaling: a thicker liner improves barrier and fill reliability margin, while a thinner liner preserves more of the shrinking cross-section for low-resistivity copper. Process engineers commonly target the thinnest liner that still delivers void-free fill and adequate diffusion barrier performance, since every extra nm of liner at advanced pitches measurably raises total interconnect resistance. Resistance contribution from the liner and seed stack is typically modeled and measured together, since separating the two experimentally is difficult once copper has been plated over both, and a combined resistance budget below roughly 15% to 20% of total via resistance is a common target at the tightest qualified pitches. **Electromigration and reliability performance improve measurably with a cobalt liner relative to older tantalum-nitride-only barrier schemes, because cobalt's stronger interfacial adhesion to copper reduces void nucleation at the copper-liner interface under current stress.** A copper interconnect with a well-adhered cobalt liner can show electromigration lifetime improvements of several times over a comparable structure with a weaker-adhesion barrier, an improvement that becomes increasingly important as current density in shrinking lines continues to climb generation over generation. Liner adhesion quality is checked indirectly through electromigration stress testing, since a marginal liner-copper interface often looks acceptable in as-deposited cross-section but fails prematurely under sustained current stress. A qualified liner and seed stack is typically required to hold void nucleation below a low single-digit % failure rate across the electromigration test population before it is released to production. Electromigration stress is commonly applied at elevated temperature, often in the 250 °C to 350 °C range, with stress currents chosen to accelerate failure into a testable timeframe rather than waiting for a real-time field-equivalent duration. **The overall ALD process window, precursor chemistry, deposition temperature, and cycle count, has to be balanced simultaneously against fill performance, resistance contribution, and throughput, since optimizing any one variable in isolation tends to degrade another.** A higher deposition temperature can improve film density and lower resistivity but risks parasitic CVD-like growth that degrades conformality at the via bottom; a longer purge improves conformality but adds cycle time and reduces wafer throughput. Total cycle count for a 2 nm liner target commonly runs from several dozen to around a hundred cycles depending on per-cycle growth rate, and that cycle count directly sets tool throughput for a liner module that runs on every interconnect level in the stack. A process window is typically qualified across a temperature range of about 20 °C and a precursor dose range of a few % before drift outside either bound produces a measurable fill or resistance excursion. Throughput for a full liner-plus-seed module is generally targeted to stay within a few tens of s per wafer above the baseline PVD seed module it replaced, since a much larger cycle-time penalty would erode the cost benefit of moving to ALD in the first place, even with the fill-margin and scaling advantages it provides. | Liner/seed thickness | Trench width regime | Fill outcome | Resistance impact | |---|---|---|---| | 1 nm to 1.5 nm | Below 15 nm | Void-free with tuned bath chemistry | Lowest resistance penalty | | 1.5 nm to 2.5 nm | 15 nm to 30 nm | Reliable fill, standard process | Moderate resistance penalty | | 2.5 nm to 3 nm | Above 30 nm | Highest fill margin | Resistance penalty less critical | ```flowchart Deposit ALD Co liner conformally on barrier surface → Deposit ALD Ru seed on Co liner → Verify seed continuity at via bottom → Electroplate Cu with bottom-up biased bath chemistry → Anneal and planarize by CMP → Qualify resistance contribution vs pitch → Stress test electromigration lifetime and adhesion ``` Viewed through a liner-scaling interconnect engineering lens, the cobalt ALD liner and ruthenium seed exist to solve one narrow but critical problem: keep the copper fill void-free and the barrier intact at dimensions where PVD simply cannot reach, while giving up as little of the shrinking via's resistance budget as possible to the liner itself.