contact resistance scaling
**Contact Resistance Engineering** is the **CMOS process discipline focused on minimizing the electrical resistance between the metal interconnect and the transistor source/drain — where at the 3 nm node, contact resistance (Rc) has surpassed channel resistance as the dominant component of total transistor on-resistance, requiring ultra-high S/D doping (>10²¹ cm⁻³), atomically thin interfacial barriers, and advanced metallization schemes to reduce specific contact resistivity below 1×10⁻⁹ Ω·cm² and prevent contacts from negating the transistor performance gains of each new technology generation**.
**Why Contact Resistance Dominates**
As transistors scale:
- Channel resistance decreases (shorter channel, better electrostatics).
- Contact area shrinks proportionally with device pitch.
- Rc scales as: Rc = ρc / Ac, where ρc is specific contact resistivity (Ω·cm²) and Ac is contact area.
- At 7 nm: contact width ~15 nm. At 3 nm: ~8-10 nm. Contact area shrinks ~4× from 7 nm to 3 nm.
- If ρc stays constant, Rc quadruples. With channel resistance shrinking, Rc becomes 50-70% of total Ron.
**Contact Resistivity Target by Node**
| Node | Contact Area (approx.) | ρc Target | Rc per Contact |
|------|----------------------|-----------|---------------|
| 14 nm | ~200 nm² | 5×10⁻⁹ Ω·cm² | ~25 Ω |
| 7 nm | ~100 nm² | 2×10⁻⁹ Ω·cm² | ~20 Ω |
| 3 nm | ~50 nm² | 1×10⁻⁹ Ω·cm² | ~20 Ω |
| Sub-2 nm | ~30 nm² | <5×10⁻¹⁰ Ω·cm² | <17 Ω |
**Silicide Evolution**
The metal-semiconductor contact uses a silicide (metal-Si compound) to reduce the Schottky barrier:
- **NiSi (7 nm+)**: Nickel silicide, low resistivity, well-established. Contact formed by depositing Ni, annealing to react with Si, stripping unreacted Ni.
- **TiSi (3 nm)**: Titanium silicide revived for advanced nodes. Ti has a lower Schottky barrier to n-type Si:P than Ni, reducing ρc.
- **MIS Contact**: Metal-Insulator-Semiconductor. A sub-1 nm dielectric (TiO₂, ZnO) inserted between metal and Si depins the Fermi level and reduces the effective Schottky barrier height. Experimental — potential path to <5×10⁻¹⁰ Ω·cm².
**Wrap-Around Contact (WAC) for GAA**
In GAA nanosheet transistors, the source/drain contact can wrap around the merged S/D epitaxial region, increasing the effective contact area:
- Instead of contacting only the top surface, the metal contact surrounds the S/D from three or four sides.
- Increases Ac by 2-3× compared to top-only contact.
- Requires conformal dielectric removal and metal fill around the S/D.
- TSMC N2 (2 nm) reportedly adopts WAC to manage contact resistance.
**Critical Process Parameters**
- **S/D Doping**: Active dopant concentration must exceed 5×10²⁰ cm⁻³ (PMOS B) or 3×10²¹ cm⁻³ (NMOS P). Metastable supersaturation followed by millisecond anneal (laser or flash) maximizes active concentration.
- **Pre-Clean**: Native oxide on Si S/D surface must be completely removed before silicide deposition. SiCoNi (remote plasma) or Siconi dry etch removes <1 nm oxide selectively.
- **Metal Deposition**: PVD Ti or CVD TiCl₄ for silicide precursor. Uniformity and step coverage into narrow contact holes are critical.
- **Contact Metal Fill**: W (tungsten), Co (cobalt), or Ru (ruthenium) fills the contact hole after silicide formation. At sub-10 nm contact CD, the contact metal resistivity and liner thickness dominate the total via resistance.
Contact Resistance Engineering is **the scaling bottleneck that determines whether transistor improvements actually reach the circuit level** — the interface engineering challenge where semiconductor physics, materials science, and process integration converge to manage the atomic-scale metal-semiconductor junctions that every electron in a chip must traverse.