source drain contact resistance

**Source/Drain Contact Technology** is the **interface engineering discipline that creates low-resistance electrical connections between metal interconnects and the highly-doped semiconductor source/drain regions of transistors — where contact resistivity has become the dominant component of total transistor series resistance at advanced nodes, with every 10% reduction in contact resistance translating to ~2-4% improvement in drive current and circuit performance**. **Why Contact Resistance Dominates** As transistors scale, channel resistance decreases (shorter channels, higher mobility), but contact resistance decreases much more slowly because it depends on the semiconductor-metal interface physics at atomic scale. At the 3 nm node, contact resistance constitutes 40-60% of total source/drain resistance, up from <10% at the 90 nm node. **Contact Resistivity Components** Total contact resistance = ρ_c / A_contact + R_spreading, where: - **ρ_c (specific contact resistivity)**: Depends on the metal-semiconductor barrier height (ϕ_B) and semiconductor doping concentration (N_D). ρ_c ∝ exp(ϕ_B / √N_D). Target: <1×10⁻⁹ Ω·cm². - **A_contact (contact area)**: Shrinks with scaling — smaller contact area means higher resistance for the same ρ_c. At 3 nm: contact area ~100-200 nm² per source/drain. **Silicide Technology** A metal silicide layer between the metal contact and silicon reduces the Schottky barrier: - **TiSi₂** → **CoSi₂** → **NiSi** (evolution over nodes). NiSi has been the workhorse from 65 nm to 14 nm. - **Ti-Based Silicide Revival**: At FinFET/GAA nodes, Ti silicide (TiSi or Ti-based) is preferred because it forms at lower temperatures (compatible with thermal budgets) and provides lower contact resistance to highly-doped SiGe (PMOS) and Si:P (NMOS). **Advanced Contact Schemes** - **Wrap-Around Contact (WAC)**: For GAA nanosheets, the contact metal wraps around the source/drain epitaxy, maximizing contact area. Unlike FinFET where the contact touches only the top and sides of the epitaxial diamond shape, WAC exploits the GAA geometry to contact from more directions. - **Contact Over Active Gate (COAG)**: Place the S/D contact overlapping the gate region (with insulating gate cap separating them). Reduces contacted poly pitch (CPP), enabling smaller standard cells and higher logic density. Requires precise self-aligned contact etch. - **Direct Metal Interface**: Research into barrier-height-free contacts using semi-metallic contacts (MIS — Metal-Insulator-Semiconductor with ultra-thin insulator tunneling) that achieve near-zero Schottky barrier. **Doping Engineering for Low ρ_c** Contact resistivity decreases exponentially with doping concentration. Targets: - **NMOS (Si:P)**: Active P concentration >5×10²⁰ cm⁻³. Limited by P solid solubility and deactivation during thermal processing. - **PMOS (SiGe:B)**: Active B concentration >3×10²⁰ cm⁻³ in SiGe with >30% Ge. Higher Ge content lowers the valence band offset, reducing barrier height. - **Dopant Activation**: Millisecond laser or flash annealing achieves maximum activation with minimal diffusion. Nanosecond laser annealing (melt-recrystallization) can achieve super-equilibrium active concentrations. Source/Drain Contact Technology is **the atomic-scale interface that connects the quantum world of transistor channels to the classical world of metal wires** — where the physics of electron tunneling through potential barriers at the metal-semiconductor junction determines how much of the transistor's intrinsic switching speed actually reaches the circuit level.