Computer Architecture

Computer architecture is where the gates and registers from digital logic finally get assembled into a working CPU, and it also returns to the fetch-decode-execute cycle this series introduced in its very first topic, now explained in real depth. An instruction is a single operation the CPU knows how to perform — add two numbers, load a value from memory, compare two registers — encoded as raw binary exactly as covered in data representation; assembly language is a thin, human-readable layer directly on top of that binary, one line per instruction, with mnemonics like ADD or LOAD standing in for the actual bit patterns, which is as close to the hardware as a programmer can get without writing 1s and 0s by hand. The CPU executes instructions through the repeating fetch, decode, execute cycle already named in this series' first topic: fetch pulls the next instruction from memory using a register, decode figures out which operation it specifies and which registers or memory addresses it touches, and execute actually performs it — addition and comparison run through an arithmetic logic unit built directly from the half-adders and full-adders of digital logic, while a control unit, also just more logic gates, sequences the whole cycle and decides which hardware components get used on any given step. A register, already introduced as a handful of flip-flops, is the CPU's fastest possible storage — reading or writing one register costs a single clock cycle, with nothing faster available on the chip. A cache sits directly between the registers and main memory as a small, fast layer that keeps a copy of recently used data, because RAM access is dramatically slower than a register and most programs reuse the same small set of data and instructions repeatedly, a principle called locality, so a cache hit is far cheaper than a cache miss, where the CPU has to wait for RAM instead. The memory hierarchy arranges every storage tier available to a computer — registers, then cache, then RAM, then disk, the same two tiers introduced back in the very first topic of this series — from fastest-and-smallest at the top to slowest-and-largest at the bottom, and every tier below the top exists purely as a cost tradeoff: faster memory is dramatically more expensive per byte, so a real system layers cheap, large, slow storage underneath small amounts of expensive, fast storage and relies on locality to keep the common case fast. This entire chapter — instructions, the fetch-decode-execute cycle, and the memory hierarchy that feeds it — is the hardware picture the next topic, operating systems, has to manage and share safely across every program running on the machine at once.