contact resistivity
**Contact Resistivity and Silicide Engineering at Advanced Nodes** is the **set of materials science and process techniques used to minimize the electrical resistance at the metal-to-semiconductor junction in CMOS transistors** — where contact resistance has become the dominant component of total transistor series resistance at sub-7nm nodes, with the metal-semiconductor interface resistivity (ρc) needing to drop below 1 × 10⁻⁹ Ω·cm² to prevent contacts from limiting transistor drive current.
**Contact Resistance Dominance**
| Node | Total S/D Resistance | Contact % of Total | Channel % |
|------|---------------------|-------------------|-----------|
| 45nm | ~300 Ω·µm | ~20% | ~50% |
| 14nm FinFET | ~200 Ω·µm | ~40% | ~30% |
| 7nm | ~180 Ω·µm | ~55% | ~20% |
| 5nm/3nm | ~160 Ω·µm | ~65% | ~15% |
| GAA 2nm | ~150 Ω·µm | ~70% | ~10% |
**Contact Resistance Components**
```
[Metal plug (W or Co or Ru)]
|
[Metal-silicide interface] ← Contact resistivity ρc
|
[Silicide (TiSi₂ or NiSi)] ← Silicide sheet resistance
|
[Doped S/D semiconductor] ← Spreading resistance
```
- ρc (interfacial): Dominant at advanced nodes → needs exponential improvement.
- Goal: ρc < 1 × 10⁻⁹ Ω·cm² (10⁻⁹ = 1 nΩ·cm²).
- Current best: ~2-5 × 10⁻⁹ Ω·cm² → still limiting.
**Silicide Materials Evolution**
| Silicide | Resistivity | Barrier Height (n-Si) | Era |
|---------|------------|----------------------|-----|
| TiSi₂ | 13-16 µΩ·cm | 0.60 eV | Pre-90nm |
| CoSi₂ | 14-18 µΩ·cm | 0.64 eV | 90-45nm |
| NiSi | 10-14 µΩ·cm | 0.65 eV | 45-14nm |
| NiPtSi | 12-15 µΩ·cm | 0.63 eV | 14-7nm |
| TiSi (amorphous) | 15-20 µΩ·cm | 0.50 eV | 7nm+ |
**Schottky Barrier Lowering Methods**
- **High doping**: Higher S/D doping → thinner depletion width → more tunneling → lower ρc.
- Target: >5 × 10²⁰ /cm³ for both N and P.
- Limit: Solid solubility limit of dopants in Si.
- **Dopant segregation**: Implant dopant (As, P, B) at silicide/Si interface → accumulation → barrier thinning.
- **Dipole engineering**: Insert thin insulator (TiO₂ for NMOS, ZnO for PMOS) at interface → dipole lowers barrier.
- **Alternative contact metals**: Low barrier height metals (Ti for NMOS, Ni for PMOS).
**Wrap-Around Contact (WAC)**
- Contact wraps around S/D epi → larger contact area → lower total resistance.
- Contact area: Top + sidewalls of S/D → 2-3× more area than top-only.
- Challenge: Etch-back to expose S/D sidewalls without damaging gate spacer.
- GAA integration: WAC for each nanosheet S/D → further increases contact area.
**Contact Plug Metallization**
| Metal | Resistivity | Fill Method | Node |
|-------|-----------|------------|------|
| W (tungsten) | 5.3 µΩ·cm | CVD (WF₆ + H₂) | Established |
| Co (cobalt) | 6.2 µΩ·cm | CVD (barrier-free) | 10nm+ |
| Ru (ruthenium) | 7.1 µΩ·cm | ALD (barrier-free) | 5nm+ |
| Mo (molybdenum) | 5.3 µΩ·cm | ALD | 3nm+ |
**Key Research Directions**
- Semi-metal contacts: Bi₂Se₃, Sb₂Te₃ → zero Schottky barrier → theoretical ρc → 10⁻¹⁰ Ω·cm².
- Fermi-level depinning: Remove metal-induced gap states → barrier follows metal work function.
- Epitaxial contacts: Grow metal epitaxially on Si → atomically clean interface.
Contact resistivity engineering is **the single most critical resistance-reduction challenge in advanced CMOS** — as transistor channels become shorter and more conductive through strain and mobility engineering, the metal-semiconductor contact has become the dominant bottleneck that limits how much current a transistor can deliver, making sub-nΩ·cm² contact resistivity the holy grail of interconnect research at every leading-edge semiconductor company.