Double Diffused Silicon Mesa 1956 Select Prepare Wafer

# Select and Prepare the Starting Silicon Wafer: Choosing the Crystal That Will Carry a Field It Doesn't Yet Have

## 1. Why Silicon's Resistivity Has to Be Chosen Before Anything Else Happens

Every later step in this process — both diffusions, the drift field they create, the mesa etch, the final cutoff frequency — is bounded by a decision made before a single dopant atom is introduced: the resistivity and orientation of the starting N-type silicon itself. The wafer serves as the collector region of the finished transistor, and its background doping concentration $N_D$ sets the breakdown voltage and the depletion width the device will have once it is finished. Too lightly doped, and series resistance in the collector wastes gain; too heavily doped, and breakdown voltage collapses and the depletion region the base-collector junction needs to support becomes too thin. The resistivity target is chosen as a tradeoff:

$$\rho = \frac{1}{q \mu_n N_D}$$

where $q$ is the electron charge and $\mu_n$ is electron mobility in silicon. A typical float-zone or Czochralski N-type wafer for this process is specified in the few-ohm-cm to tens-of-ohm-cm range, with crystal orientation fixed (commonly $\langle 111 \rangle$ for this era) so that later etch steps expose predictable crystallographic planes at the mesa sidewall.

From a Grown Crystal to a Resistivity-Specified Wafer the one upstream choice that bounds every downstream electrical property of this device GROWN SILICON BOULE N-type dopant: phosphorus wafer slice sliced perpendicular to the growth axis RESISTIVITY & ORIENTATION SPEC ρ = 1 / (q · μₙ · Nᵈ) target: a few Ω·cm to tens of Ω·cm lower Nᵈ → higher breakdown, more series resistance donor concentration Nᵈ orientation fixed, commonly 〈111〉, so the later mesa etch exposes a predictable crystal plane this one spec bounds breakdown voltage, series resistance, and etch behavior for every step that follows

## 2. Real Diagram: What the Wafer Physically Is Before Any Process Step Touches It

A finished wafer at this stage is simply a thin, flat, single-crystal disk of uniformly doped N-type silicon — no junctions, no mesa, no metal. It is the blank canvas every later step will modify. The diagram below shows the wafer in cross-section exactly as it leaves this step: uniform doping throughout its thickness, a specified crystal orientation at the surface, and nothing else.

Cross-Section: the Wafer as It Leaves This Step uniform N-type bulk, no junction yet exists anywhere in this slab uniform N-type silicon, Nᵈ constant with depth this bulk region becomes the collector of the finished transistor depth into the wafer, surface at top polished surface, 〈111〉 orientation no base, no emitter, no field, no mesa — every one of those is still an unassigned future step this diagram is the entire process's starting condition, not yet its first transformation

## 3. Why This Step Is Different From the Germanium Starting Material in the 1954 Process

The 1954 diffused-base process this project has already documented began from high-purity germanium for the same structural reason — a clean, defect-free, correctly doped starting crystal is the precondition for every diffusion that follows. What changes here is the material itself and what that material choice is actually buying: germanium's narrower bandgap

$$E_{g,\text{Ge}} \approx 0.67\ \text{eV} \quad \text{vs.} \quad E_{g,\text{Si}} \approx 1.12\ \text{eV}$$

means intrinsic carrier concentration, and therefore leakage current, rises far faster with temperature in germanium than in silicon. Choosing silicon at this very first step is what makes the entire later process capable of producing a device that survives well past the roughly 75°C ceiling germanium devices run into — a consequence this project's germanium series could never reach no matter how the later diffusion steps were tuned, because the limitation was set by the starting material, at this step, before any diffusion occurred at all.

Step 1 does not create a transistor; it selects and commits to the one material property — bandgap — that determines how hot every transistor built from this wafer will ever be allowed to run.

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