design for debug
**Design-for-Debug (DfD) Infrastructure** is the **set of on-chip hardware structures (trace buffers, trigger logic, performance counters, and debug buses) built into a chip to enable post-silicon debugging of functional bugs, performance issues, and system-level integration problems** — providing visibility into internal chip state that would otherwise be invisible after the chip is packaged, where the investment of 3-5% die area for debug infrastructure can save months of debug time and prevent costly re-spins caused by undiagnosed silicon bugs.
**Why DfD Is Essential**
- Pre-silicon simulation: Covers <1% of possible states → bugs remain.
- First silicon: ~50-80% of chips have bugs requiring debug.
- Without DfD: Bug manifests as incorrect output → no visibility into why → weeks/months of guesswork.
- With DfD: Trigger on condition → capture internal signals → root cause in days.
**DfD Components**
| Component | What It Does | Overhead |
|-----------|-------------|----------|
| Trace buffer | Records internal signals over time | 0.5-2% area (SRAM) |
| Trigger logic | Detects specific events/conditions | 0.1-0.5% area |
| Debug bus/MUX | Routes selected signals to trace | 0.2-1% area + wires |
| Performance counters | Count events (cache misses, stalls, etc.) | 0.1-0.3% area |
| JTAG/debug port | External access to debug infrastructure | Minimal |
| Bus monitor | Snoop on-chip bus transactions | 0.2-0.5% area |
**Trace Buffer Architecture**
```
Internal signals (hundreds)
↓
[Debug MUX] ← selects which signals to observe (programmable)
↓
[Compression] ← optional: compress trace data
↓
[Trigger Unit] ← start/stop capture on event match
↓
[Trace SRAM] ← stores last N cycles of selected signals
↓
[JTAG readout] → off-chip analysis
```
- Trace width: 64-256 bits (selected from thousands of internal signals).
- Trace depth: 1K-64K entries → records 1K-64K cycles of history.
- Trigger: Programmable match on address, data, FSM state → start/stop capture.
- Post-trigger: Capture N cycles after trigger → see events after bug condition.
- Pre-trigger: Circular buffer → see events leading up to bug.
**Trigger Logic**
| Trigger Type | What It Detects |
|-------------|----------------|
| Address match | Specific memory address accessed |
| Data match | Specific data value on bus |
| Event sequence | Event A followed by Event B within N cycles |
| Counter threshold | Cache miss count exceeds limit |
| Watchpoint | Write to protected memory region |
| Cross-trigger | Trigger from another IP block |
**Performance Counters**
- Programmable counters that count hardware events.
- Events: Cache hits/misses, branch predictions, pipeline stalls, bus transactions.
- Software reads counters via performance monitoring unit (PMU) registers.
- Use: Performance profiling (perf, VTune), power estimation, workload characterization.
- Typical: 4-8 programmable counters per core + fixed counters for cycles/instructions.
**Debug Modes**
| Mode | Mechanism | Speed | Use Case |
|------|-----------|-------|----------|
| JTAG scan | Stop clock, shift out state | Very slow (KHz) | Full state dump |
| Trace capture | Record at speed, read out later | Full speed | Race conditions, timing bugs |
| Logic analyzer (ATE) | External probe | Near-speed | Manufacturing debug |
| Software debug (breakpoint) | CPU halts at address | Full speed until break | Firmware debug |
**Area and Power Trade-off**
- Trace SRAM: 32KB trace buffer → ~0.03mm² at 5nm → acceptable.
- Debug MUX and trigger: ~0.5-1% of block area.
- Power: Debug infrastructure can be clock-gated when not in use → zero active power.
- Trade-off: 3-5% total area overhead → saves weeks of debug time + potential re-spin ($10M+).
Design-for-debug infrastructure is **the insurance policy that makes first-silicon bring-up feasible within weeks instead of months** — without trace buffers, trigger logic, and performance counters, post-silicon debugging of subtle functional bugs and performance anomalies would require blind guessing from external observations alone, making DfD one of the most cost-effective investments in the entire chip design process.