design for test
**Design for Test (DFT) Methodology** is the **systematic insertion of test structures and circuit modifications during the design phase that make the manufactured chip observable and controllable for manufacturing testing** — transforming an opaque silicon die into one where internal nodes can be set and measured, enabling the detection of physical defects that would otherwise escape to the customer and cause field failures.
**Why DFT?**
- Without DFT: Internal nodes of a chip are invisible — can only observe primary outputs.
- Controllability: Can you set any internal node to 0 or 1?
- Observability: Can you measure the value of any internal node?
- Without DFT: Fault coverage ~30-50%. With DFT: Fault coverage > 98%.
**DFT Techniques Overview**
| Technique | What It Tests | Overhead | Coverage |
|-----------|-------------|---------|----------|
| Scan Chain | Combinational + sequential logic | 5-15% area | 95-99% |
| LBIST | Logic (self-test) | 3-5% area | 90-95% |
| MBIST | Embedded memories | 1-3% area | 99%+ |
| JTAG / Boundary Scan | Board interconnects, chip I/O | < 1% area | 100% I/O |
| IDDQ Testing | Bridging faults, leakage | 0% (measurement) | Complementary |
| At-Speed Test | Timing defects (small delay) | Minimal | 85-95% |
**Scan Chain Architecture**
1. Every flip-flop replaced with **scan flip-flop** (MUX + FF).
2. In test mode: FFs connected in a serial shift chain.
3. **Shift-in**: Load test pattern through chain (serial).
4. **Capture**: Apply one functional clock — combinational logic evaluates.
5. **Shift-out**: Read captured response through chain (serial).
6. Compare response to expected → detect faults.
**Compression DFT**
- Problem: Million-gate chips have 1M+ scan FFs → shift time too long.
- Solution: **Scan compression** — decompressor at scan-in, compactor at scan-out.
- Compression ratio: 50-200x → reduces test data volume and test time proportionally.
- Tools: Synopsys DFTMAX, Cadence Modus, Siemens Tessent.
**DFT Flow Integration**
1. **RTL**: Architect identifies testability requirements.
2. **Synthesis**: DFT tool inserts scan chains, compression, BIST controllers.
3. **ATPG**: Generate test patterns targeting stuck-at, transition, bridge faults.
4. **Layout**: DFT-aware P&R ensures scan chains are routable.
5. **Silicon**: ATE applies patterns from ATPG → pass/fail.
**Test Economics**
- DFT area overhead: 5-15% — pays for itself by catching defective chips.
- Cost of shipping a defective chip: $1-100 (consumer) to $10,000+ (automotive/medical).
- Automotive ASIL-D requirement: > 99% fault coverage through DFT.
Design for Test is **a non-negotiable requirement for any commercial chip** — the investment in DFT infrastructure during design directly determines the quality and cost of manufacturing test, with insufficient testability leading to either expensive test escapes or prohibitively long test times.