design rule checking advanced

**Advanced Design Rule Checking (DRC)** encompasses the **increasingly complex set of geometric constraints and pattern-dependent rules at leading-edge technology nodes (5nm and below), where traditional width/space/enclosure rules are supplemented by context-dependent, multi-patterning, and EUV-specific rules** that reflect the physics of nanoscale patterning. At mature nodes, DRC was simple — minimum width, space, enclosure, area. At advanced nodes, rule count has exploded: a 3nm PDK may contain 5,000-10,000+ individual DRC rules, compared to ~500 rules at 90nm. This complexity arises from: **Multi-Patterning Rules**: SADP/SAQP and LELE decomposition impose color-assignment constraints. DRC must verify that features assigned to the same mask color satisfy the single-exposure minimum space (larger than the multi-patterning minimum space), and that decomposition is valid (no odd-cycle conflicts). Tip-to-tip rules between same-color features differ from different-color features. **EUV-Specific Rules**: EUV eliminates multi-patterning for some layers but introduces: **stochastic-aware rules** — minimum feature sizes must account for photon shot noise; **line-end extension rules** — EUV's lower contrast at feature ends requires longer extensions; and **mask 3D effect rules** — the thick absorber on EUV masks creates pattern-shift depending on feature orientation and field position. **Context-Dependent Rules**: Minimum space between two features may depend on their widths, lengths, and surrounding pattern density. These rules capture localized stress, CMP planarity, and etch loading effects. A metal line adjacent to a wide bus may require larger spacing than near another minimum-width line. **Pattern-Matching Rules**: Some DRC checks use pattern-matching (topology-based) rather than simple edge-based geometry. Prohibited patterns (known lithographic hotspots or yield failures) are encoded as pattern libraries. Recommended rules flag legal-but-risky patterns. **Grid and Alignment Rules**: All routing is on-grid at advanced nodes — tracks snap to a predefined routing grid, vias only at grid intersections. Off-grid placement is a hard DRC violation. Pin access rules specify exactly which grid positions are valid. **Verification Runtime**: DRC for a full chip at 3nm can take 12-48+ hours on a large compute cluster. Hierarchical DRC, incremental DRC, and GPU-accelerated engines are essential. **Advanced DRC has become a design methodology constraint that shapes how circuits are laid out, pushing the industry toward highly-regularized, template-based design styles where manufacturability is the primary design driver.**