design rule checking drc

Physical verification is the sign-off discipline that proves a chip layout can be manufactured and still matches the intended circuit. **DRC and LVS answer different questions.** Design rule checking asks whether the geometry obeys the foundry's manufacturing rules. Layout-versus-schematic asks whether the polygons implement the same devices and connectivity as the schematic or netlist. A design can pass one and fail the other. | Check | Question it answers | Typical failure | |---|---|---| | DRC | Can the foundry build these shapes reliably? | Spacing, width, density, antenna, or enclosure error | | LVS | Does layout match circuit intent? | Missing connection, swapped device, short, or open | | ERC | Are electrical rules respected? | Floating gate, over-voltage path, or unsafe well tie | | Antenna | Will plasma charging damage gates during fabrication? | Long metal path connected to a sensitive gate | **The foundry rule deck is part of the manufacturing contract.** Waivers should be rare, reviewed, and traceable, because every accepted violation becomes a bet that the fab can still build the design with acceptable yield and reliability.