design rule check drc
**Physical Verification (DRC/LVS)** is the **mandatory pre-tapeout verification step that validates the chip layout (GDSII/OASIS) against the foundry's manufacturing rules (Design Rule Check) and against the electrical schematic (Layout versus Schematic) — where any uncaught DRC violation can cause systematic yield loss across every die on every wafer, and any LVS mismatch means the fabricated chip will not match its intended circuit function**.
**Design Rule Check (DRC)**
Foundry design rules encode the physical constraints of the manufacturing process — minimum feature sizes, spacing requirements, enclosure rules, and density requirements that ensure the layout can be reliably manufactured with acceptable yield.
- **Width Rules**: Minimum metal width ensures wires don't break during CMP or electromigration. Maximum width prevents dishing.
- **Spacing Rules**: Minimum space between same-layer features prevents shorts caused by lithographic proximity effects. Varies with wire width (wide-metal spacing rules).
- **Enclosure Rules**: Contact/via must be enclosed by minimum overlap of connecting metal layers to guarantee reliable connectivity.
- **Density Rules**: Metal density must be within min/max bounds per layer to ensure uniform CMP polishing. Dummy fill is inserted to meet minimum density.
- **Antenna Rules**: Long connected metal before a gate connection can accumulate charge during plasma etch, damaging the thin gate oxide. Antenna ratios (metal area / gate area) must be below limits; violations fixed by adding diode connections or routing jumpers.
**Layout versus Schematic (LVS)**
LVS extracts the circuit (transistors, resistors, capacitors, connections) from the physical layout and compares it against the schematic netlist to verify functional equivalence:
- **Device Extraction**: Identifies transistors from overlapping poly, diffusion, and well layers. Measures W/L, number of fingers, and device type.
- **Connectivity Extraction**: Traces metal routing to identify the complete netlist — every node, every connection.
- **Comparison**: Extracted layout netlist is compared node-by-node against the source schematic. Any mismatch (extra device, missing connection, shorted nets, open nets) is reported.
**Common Error Categories**
| Error Type | Cause | Risk |
|-----------|-------|------|
| Metal short (DRC) | Insufficient spacing | Functional failure |
| Via enclosure (DRC) | Misaligned via | Open circuit, yield loss |
| Antenna violation (DRC) | Long metal antenna ratio | Gate oxide damage |
| Device mismatch (LVS) | Wrong transistor size/type | Circuit malfunction |
| Float net (LVS) | Unconnected wire | Unpredictable behavior |
**ERC (Electrical Rule Check)**: Additional checks layered on LVS — detecting floating gates, missing substrate connections, well/bulk connection violations, and ESD protection path integrity.
**Physical Verification is the final quality gate before committing to multi-million-dollar mask fabrication** — the automated check that catches the manufacturing-fatal errors that no amount of simulation or formal verification can detect because they exist only in the physical geometry of the layout.