physical verification drc lvs

**Physical Verification DRC/LVS Closure** is **the mandatory signoff step that validates the chip layout against manufacturing design rules (DRC) and confirms that the physical layout electrically matches the intended schematic netlist (LVS), ensuring that the design is both manufacturable and functionally correct before tapeout** — with a strict requirement of zero violations for production-quality designs. **Design Rule Checking (DRC):** - **Rule Categories**: minimum width, minimum spacing, enclosure, extension, area, density, and antenna rules for each metal layer, via, and device layer; advanced nodes add multi-patterning coloring rules, via alignment constraints, and EUV-specific overlay rules — total rule count exceeds 5,000-10,000 at sub-7nm nodes - **Width and Spacing**: minimum metal width ensures reliable fabrication without opens; minimum spacing prevents shorts between adjacent conductors; both rules tighten with each technology node and vary by metal layer and local pattern context - **Density Rules**: minimum and maximum metal density requirements ensure uniform CMP planarization; fill insertion algorithms add dummy metal shapes in sparse regions to meet density targets, typically 20-80% per metal layer - **Antenna Rules**: long metal lines connected to thin gate oxide during fabrication can accumulate plasma-induced charge that damages the gate; antenna ratios (metal area to gate area) are checked and violations are fixed by adding diode protection or breaking the antenna path with higher-layer routing **Layout Versus Schematic (LVS):** - **Extraction**: the LVS tool extracts transistors, resistors, capacitors, and diodes from the physical layout by recognizing device geometries from layer intersections; extracted devices are connected through the metal routing to form a layout netlist - **Comparison**: the extracted layout netlist is compared against the schematic (source) netlist; LVS checks device count, connectivity, device parameters (width, length, multiplicity), and net topology for exact matches - **Common Errors**: missing connections (opens), unintended connections (shorts), extra or missing devices, incorrect device sizing, and floating nets; each error requires layout correction and re-verification - **Hierarchical LVS**: large SoC designs use hierarchical verification where individual blocks are verified bottom-up and their verified abstracts are used at higher hierarchy levels; this reduces verification time from days to hours but requires consistent interface definitions **Electrical Rule Checking (ERC):** - **Well and Substrate Connections**: every N-well and P-substrate region must have adequate contact to its respective supply rail to prevent latch-up; ERC verifies well-tap density and proximity to active devices - **Floating Gates and Nodes**: unconnected gate electrodes or floating metal structures can accumulate charge and cause unpredictable device behavior; ERC flags all electrically floating nodes - **Power/Ground Connectivity**: all VDD and VSS nets are checked for proper connection to pad ring and through all hierarchy levels; missing power connections cause entire blocks to be non-functional **Signoff Flow:** - **Iterative Closure**: DRC and LVS violations are iteratively fixed, with each correction requiring re-verification to confirm the fix doesn't introduce new violations; automated fix tools handle simple violations (spacing, width) while complex issues require manual layout editing - **Waiver Management**: some DRC rules may be temporarily waived with engineering justification for known-good patterns; all waivers are documented and reviewed by the foundry before tapeout acceptance - **Final Signoff**: the foundry requires a clean DRC/LVS/ERC report as a tapeout deliverable; any remaining violations must be explicitly waived with technical justification and risk assessment Physical verification DRC/LVS closure is **the non-negotiable quality gate that prevents manufacturing defects and functional errors from reaching silicon — representing the final line of defense between design intent and physical reality, where every violation caught saves potential yield loss and costly mask re-spins**.