physical verification drc lvs

**Physical Verification (DRC/LVS)** is the **mandatory sign-off step that validates the chip layout against the foundry's manufacturing rules (DRC) and verifies that the layout implements the intended circuit connectivity (LVS) — serving as the final gate between design completion and tapeout, where a single unresolved DRC violation means the foundry will reject the design, and a single LVS mismatch means the fabricated chip will not function correctly**. **Design Rule Check (DRC)** DRC verifies that every geometric shape in the layout complies with the foundry's manufacturing design rules: - **Width Rules**: Minimum metal line width, poly gate minimum width, active area minimum width. Violations cause opens (too narrow to survive etch) or shorts (insufficient spacing). - **Spacing Rules**: Minimum distance between adjacent features on the same layer. Violations cause bridging defects. - **Enclosure Rules**: Minimum overlap of one layer over another (e.g., via enclosure by metal, contact enclosure by active). Violations cause misaligned contacts and increased resistance. - **Density Rules**: Minimum and maximum pattern density per layer within specified windows. Ensures CMP uniformity. - **Multi-Patterning Rules**: Color assignment and spacing rules for SADP/SAQP decomposition. Ensures the layout can be split into two or four masks with no coloring conflicts. - **Antenna Rules**: Maximum ratio of metal area connected to a gate during fabrication. Prevents plasma-charging damage to thin gate oxides during etch. **Layout Versus Schematic (LVS)** LVS extracts the circuit netlist from the physical layout (identifying transistors from overlapping poly and active regions, capacitors from overlapping metal plates, resistors from resistor-body layers) and compares it against the schematic netlist: - **Device Matching**: Every transistor, resistor, and capacitor in the schematic must have a corresponding device in the layout with matching parameters (W, L, number of fingers, connections). - **Connectivity Matching**: The extracted net connections must match the schematic net connections. Every signal must connect to the same set of device pins in both representations. - **LVS Clean**: Zero mismatches between extracted and schematic netlists. **Sign-Off Complexity** A modern SoC tapeout involves: - **>10,000 DRC rules** per mask layer, across 60-80 mask layers. - **DRC runtime**: 12-48 hours on a 1000-core compute cluster for a full-chip run. - **LVS runtime**: 4-24 hours with hierarchical extraction. - **Multiple DRC decks**: base DRC, density, antenna, multi-patterning, recommended rules, reliability rules. Physical Verification is **the non-negotiable quality checkpoint that separates a design from a tapeout** — the final mathematical proof that the physical layout can be manufactured by the foundry and will implement the intended circuit.