die
**Die (dicing and singulation)** refers to the **individual chip units cut from a processed semiconductor wafer** — after hundreds of fabrication steps, the wafer is sliced along scribe lines to separate each die, which is then packaged into the finished chips used in electronics.
**What Is a Die?**
- **Definition**: A single rectangular piece of a semiconductor wafer containing one complete integrated circuit — the "chip" before packaging.
- **Die Size**: Ranges from 1mm² (simple sensor) to 800mm² (large GPU/datacenter processor).
- **Per Wafer**: A 300mm wafer yields 100-5,000+ dies depending on die size and edge exclusion.
- **Scribe Lines**: Narrow lanes (50-100µm) between dies contain test structures and alignment marks — this is where the wafer is cut.
**Why Die Yield Matters**
- **Yield Definition**: Percentage of functional dies per wafer — directly determines chip manufacturing cost.
- **Cost Impact**: If a 300mm wafer costs $10,000 to process and yields 500 good dies, each die costs $20. If yield drops to 50%, cost doubles to $40/die.
- **Defect Sensitivity**: Larger dies have lower yield because each defect has a higher probability of landing on the die — this is why chiplets and multi-die designs are increasingly popular.
- **Yield Learning**: New process nodes start with low yield (30-50%) and improve to 80-95%+ over months of optimization.
**Dicing Methods**
- **Diamond Blade Dicing**: Traditional method — a thin diamond-coated blade spins at 30,000-60,000 RPM and cuts through the wafer along scribe lines. Fast and economical.
- **Laser Dicing**: Focused laser beam scribes or ablates the silicon — less mechanical stress, better for thin wafers and low-k dielectrics.
- **Stealth Dicing (SD)**: Laser creates internal modification layer, then wafer is expanded to cleave — zero kerf loss, minimal chipping.
- **Plasma Dicing**: Uses deep reactive ion etch (DRIE) to etch through scribe lines — handles irregular die shapes and very thin wafers (<100µm).
**Die Yield Calculation**
| Metric | Formula | Typical Value |
|--------|---------|---------------|
| Gross Die per Wafer | π × (r-edge)² / die_area | 100-5,000 |
| Die Yield | Good dies / Gross dies × 100% | 70-95% |
| Wafer Yield | Good wafers / Total wafers × 100% | 95-99% |
| Defect Density (D0) | Defects per cm² | 0.05-0.5 |
**Post-Dicing Steps**
- **Die Sorting**: Automated optical and electrical inspection separates good dies from defective ones.
- **Die Attach**: Good dies are bonded to package substrates using epoxy or solder.
- **Wire Bonding / Flip-Chip**: Electrical connections made from die pads to package leads.
- **Encapsulation**: Die is protected with molding compound or lid.
Die yield is **the single most important economic metric in semiconductor manufacturing** — it directly determines whether a chip product is profitable and drives continuous improvement efforts across every fab in the world.