DRAM-1968 Step 12 Confront Sense Amplifier Bit Line Topology Choice

# Confront the Sense-Amplifier Choice: Open Bit Line Versus Folded Bit Line

Step 7 established that reading a 1T1C cell shares its charge onto a bit line and requires sensing and restoration; it did not say how that bit line is physically paired with a reference for sensing, and that pairing choice carries its own tradeoff.

## 1. State the Two Topologies Step 7 Left Unresolved

An open bit-line array pairs a selected cell's bit line against a reference bit line from an *adjacent* array block, on the opposite side of the sense amplifier. A folded bit-line array instead routes both the selected bit line and its reference line from *within the same array block*, folding the layout so both lines run side by side into one sense amplifier. Both achieve the same electrical goal Step 7 described — a differential signal the amplifier can resolve — by different physical routing.

Confront the Sense-Amplifier Choice: Open Bit Line Versus Folded Bit L Step 12 — dram-1968 State the Two Topologies Step 7 Left Unresolved see Section 1 Weigh Noise Rejection Against Array Efficiency see Section 2 Confirm This Is a Periphery Decision, Not a Cell see Section 3 THREE-PART ARGUMENT, ONE STEP dram-1968 extension, step 12 of this project's DRAM lineage

## 2. Weigh Noise Rejection Against Array Efficiency

Folded bit-line pairs two adjacent lines that have nearly identical parasitic coupling to neighboring word lines and substrate noise, so common-mode disturbances cancel well in the differential sense — a real noise-rejection advantage open bit-line, with its reference line physically remote, does not share as cleanly. Open bit-line's advantage is array efficiency: it does not need the extra routing folded bit-line spends to keep both lines of a pair physically adjacent, so it can pack more sense amplifiers per unit array width. Neither topology is simply "better"; later generations (including the 64K-era periphery work this project's own `dram64k_1979` series covers under a different name — row/column addressing, not sense topology) adopted folded bit-line specifically as refresh-margin pressure from shrinking $C_s$ made noise rejection the deciding factor.

Step 12 in the Dram-1968 Lineage what this step inherits and what it hands forward, by name Step 12 this step Inherits prior steps Hands Off named thread NO CELL-PHYSICS OR ARCHITECTURE RE-ARGUED each step adds a distinct angle; none re-derive settled prior content

## 3. Confirm This Is a Periphery Decision, Not a Cell Decision

Neither topology changes anything about the cell this series built in Steps 2 through 4, or the leakage and retention physics in Steps 5 through 7. It is a decision made once, at the array's edge, about how many cells share one amplifier and how that amplifier's two inputs are routed — the same kind of periphery-level decision this project's `dram64k_1979` series treats more fully for addressing and refresh scheduling specifically, not sensing.

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