DRAM 1968 Confront Destructive Readout Restore Cell Charge

# Confront Destructive Readout: Reading the Cell Disturbs the Charge Being Read

## 1. The Bit Cannot Be Observed Without Connecting It to a Much Larger Electrical Node

A 1T1C cell has no buffered output: reading it requires turning on the access transistor and connecting the storage capacitor directly to the column bit line. The bit line is not an ideal voltmeter with infinite input resistance and zero capacitance. It is a long conductor shared by many cells, with its own capacitance $C_{BL}$ and a prepared voltage $V_{pre}$. When the word line rises, charge redistributes between the cell and that line until both reach a common voltage.

Charge conservation gives the immediate shared voltage:

$$V_{share}=\frac{C_sV_s+C_{BL}V_{pre}}{C_s+C_{BL}}$$

and the bit-line signal relative to its prepared level is

$$\Delta V_{BL}=V_{share}-V_{pre}=\frac{C_s}{C_s+C_{BL}}\left(V_s-V_{pre}\right)$$

Because $C_{BL}$ is generally larger than one cell capacitor, the observable bit-line change is only a fraction of the original cell-to-precharge difference. At the same time, the cell voltage is pulled to $V_{share}$. The act that reveals the state therefore changes the state.

Readout Is Charge Sharing, Not Passive Observation raising the word line forces the cell and bit line to one intermediate voltage BEFORE WL RISES · ISOLATED bit line at V_pre FET OFF C_s at V_s two separate voltages cell charge still represents the written state AFTER WL RISES · CONNECTED FET ON charge redistributes cell and BL both settle at V_share the original V_s no longer remains on C_s ΔV_BL carries the evidence, but V_share replaces the cell's original voltage the read produces a usable clue only by partially consuming the stored condition

## 2. Sensing Must Be Followed by Restoration Before the Word Line Falls

The small $\Delta V_{BL}$ is not yet a full logic level. Shared peripheral sensing circuitry must decide which side of the prepared reference the bit line moved toward, amplify that difference to a full electrical state, and drive the bit line accordingly. While the selected word line remains active, that driven bit line charges or discharges the cell capacitor back to the decided state. Only after restoration may the word line fall and isolate a valid bit again.

A Complete Read Includes Its Own Repair precharge → share → sense → restore → isolate 1 · PRECHARGEprepare bit line 2 · SHAREWL rises, ΔV appears 3 · SENSEamplify decision 4 · RESTORErewrite through FET 5 · ISOLATEWL falls cell is disturbed throughout this interval a read is complete only after the selected capacitor has been restored dropping WL immediately after sensing would preserve V_share, not the original full-margin state

## 3. Destructive Readout Is the Second System Cost of Removing the Latch

Refresh repairs gradual leakage even when software never requests the data. Read restoration repairs the immediate disturbance created when software does request it. Both obligations arise from the same architectural choice: the cell stores an analog quantity on an unbuffered capacitor instead of maintaining a locally regenerated latch state.

The peripheral sense-and-restore circuit may be shared across many cells, preserving the cell's density advantage, but its timing is inseparable from correct operation. Word-line duration must allow charge sharing, sensing, and restoration; the bit line must then return to its prepared condition before another row uses it. A read is therefore a sequence of physical state transitions, not a nondestructive glance at a stable node.

Step 7 closes the operating loop around the 1T1C cell: write charge, isolate it, refresh before leakage removes it, and restore it whenever reading disturbs it. Step 8 now measures what this complexity purchased—the cell-area advantage over a six-transistor latch.

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