DRAM 1968 Confront Leakage Charge Does Not Stay Forever

# Confront Leakage: Why the Charge Does Not Stay Forever

## 1. The Same Off-State Current That Was Negligible for CMOS Logic Is Now the Central Failure Mechanism

The 1963 CMOS series could call subthreshold current a small correction to near-zero static power; the 1T1C cell must treat that same nonzero current as a clock that steadily destroys its information. After the word line turns the access transistor off, the storage node is isolated only ideally. A real MOS channel still passes subthreshold current, the storage-node junction passes reverse leakage into the substrate, and the capacitor dielectric is not a perfect insulator. Each path may be small, but all of them remove or add charge to a node whose entire information content is a finite $Q_s$.

$$\frac{dQ_s}{dt}=-I_{leak,total}, \qquad I_{leak,total}=I_{sub}+I_{junction}+I_{dielectric}+I_{other}$$

The sign of an individual current depends on stored state and bias convention; the governing fact is that net leakage moves the storage node away from its written condition. A current too small to matter as steady-state CMOS power can still become decisive when it acts continuously on a tiny capacitor between accesses.

The Isolated Storage Node Has More Than One Escape Path word line low removes intentional access, not physical leakage BIT LINE ACCESS FET OFF WL unselected STORAGE NODE Q_s storage capacitor PLATE V_p I_sub beneath nominally off gate I_junction reverse-biased diffusion to substrate I_dielectric through imperfect insulating film FET off does not mean I = 0: every leakage component changes Q_s over time the stored bit fails when the remaining node condition can no longer be distinguished reliably

## 2. Leakage Converts a Stored State into a Time-Dependent State

If net leakage is approximately constant over a limited voltage interval, the charge margin falls linearly:

$$Q_s(t)\approx Q_s(0)-I_{leak,total}t$$

and the corresponding storage-node voltage changes by

$$V_s(t)-V_s(0)\approx-\frac{I_{leak,total}}{C_s}t$$

This simple relation exposes the cell's basic vulnerability: less capacitance produces more voltage drift for the same leakage current, while more leakage consumes a fixed charge margin faster. Actual leakage varies with node voltage, device bias, process variation, and temperature, so the real decay need not be a straight line. The approximation is useful because it identifies the quantities the next step must measure rather than pretending the off state is infinite resistance.

A Written Charge State Shrinks Toward the Decision Boundary leakage turns memory into a race against elapsed time elapsed time after WL turns off storage-node charge Q_s minimum reliable charge margin Q_s(t) retention limit initial usable charge margin smaller C_s or larger I_leak produces a steeper voltage loss and an earlier crossing

## 3. Dynamic Memory Is Defined by Accepting Leakage and Managing It Explicitly

A latch uses positive feedback to restore its own state continuously while power remains applied. The 1T1C cell deliberately removed that local restoration to gain density. Leakage is therefore not an accidental flaw added to an otherwise static cell; it is the direct system consequence of replacing a regenerative latch with stored charge. The architecture wins area by moving responsibility for preservation out of every cell and into shared peripheral operations.

The relevant leakage is also a population problem. Subthreshold current, junction leakage, dielectric quality, stored voltage, and temperature vary from cell to cell across a wafer. An array cannot schedule preservation around an ideal or average cell if weaker cells lose their margin sooner. It must establish a safe interval that protects the required population under specified operating conditions.

Step 5 has identified why the bit decays and which currents consume it. Step 6 now measures the time from a completed write to the loss of an acceptable sensing margin, then turns that measured retention limit into a refresh interval.

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