DRAM 1968 Measure Retention Time Set Refresh Interval

# Measure the Retention Time and Set the Refresh Interval

## 1. Retention Time Is Measured from a Completed Write to the Last Reliable Read

Step 5 established that leakage continuously consumes the stored charge; this step turns that mechanism into an operating limit by measuring how long a written cell remains distinguishable. The experiment writes a known state, lowers the word line to isolate the storage node, waits for a controlled delay, and then reads the cell. Repeating the experiment with progressively longer delays locates the boundary between reliable recovery and failure.

Each delay point must begin with a fresh write. Reading couples the cell back to the bit line and changes the stored condition, so reading one cell repeatedly would measure the disturbance caused by earlier reads as well as leakage during the wait. A retention sweep instead performs independent write–wait–read trials across delays, states, cells, temperatures, and relevant bias conditions.

For the constant-leakage approximation introduced in Step 5, the first-order retention estimate is

$$t_{ret}\approx\frac{\Delta Q_{usable}}{I_{leak,total}}=\frac{C_s\Delta V_{usable}}{I_{leak,total}}$$

where $\Delta Q_{usable}$ is the charge that may be lost before the sensing margin becomes unacceptable. This equation predicts the direction of the result; the measured pass/fail boundary remains authoritative because real leakage changes with voltage, temperature, process variation, and stored state.

Retention Characterization Uses Independent Write–Wait–Read Trials every delay begins from a freshly restored storage state WRITE establish Q_s(0) WAIT Δt WITH WL OFF stored charge drifts under leakage READ ONCE pass or fail LOG Δt SWEEP DELAY AND CONDITIONS short → long Δtboth stored states many cells / locationstemperature corners voltage corners last passing delay before an unacceptable read = measured retention limit for that condition

## 2. The Refresh Interval Must Protect the Weak Tail, Not the Average Cell

An array contains a distribution of retention times because capacitance, threshold voltage, junction leakage, oxide quality, and local defects vary across cells. Temperature and bias move that distribution again. The refresh interval therefore cannot be set from a typical cell or the center of a histogram. It must remain below the qualified lower bound for the population and conditions the product promises to support.

$$t_{REF}\leq\frac{t_{ret,min,qualified}}{M_{guard}}, \qquad M_{guard}>1$$

Here $t_{ret,min,qualified}$ is the minimum accepted retention time after applying the test coverage and product criteria, while $M_{guard}$ absorbs uncertainty, operating drift, and scheduling tolerance. This expression is a design rule rather than a universal numerical interval: the safe value follows from measured silicon and the stated qualification envelope.

Refresh Is Set Left of the Qualified Retention Boundary the weakest accepted cells and worst supported conditions govern the schedule retention time → cell population measured retention distribution t_ret,min,qualified t_REF guard band refresh before the earliest qualified loss of sensing margin typical retention describes the center; product reliability is controlled by the protected tail

## 3. Refresh Converts an Analog Decay Limit into a Repeating Digital Obligation

Once $t_{REF}$ is chosen, shared peripheral circuitry must revisit every row before its cells exceed that interval. The operation senses the stored state and restores full charge, resetting the retention clock. Density was gained by removing continuous regenerative feedback from each cell, but preservation did not disappear—it became a scheduled array-level responsibility consuming time, energy, and control logic.

Retention qualification must therefore state its conditions. A number without temperature, supply, stored pattern, elapsed-time definition, pass criterion, and population coverage is not a complete retention specification. The refresh schedule must also account for the time required to traverse all rows, not merely the interval assigned to a single row.

Step 6 has established when preservation must occur, but it has not yet explained what the read itself does to the capacitor. Step 7 confronts that second disturbance: connecting the cell to the bit line redistributes its charge, so sensing must be followed by write-back.

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