DRAM 1968 Store Bit as Capacitor Charge Not Transistor Latch

# Store a Bit as Charge on a Capacitor, Not as a Latch of Transistors: Dennard's Radical Simplification

## 1. Replace a Circuit That Continuously Defends Its State with One Physical Quantity

The decisive move in Robert Dennard's 1968 IBM memory was not merely reducing a memory cell's transistor count; it was changing what physically represents the bit. A transistor latch stores state as a self-reinforcing circuit condition: multiple active devices remain cross-coupled so that one side continuously holds the other side in its opposite state. Dennard instead let the bit be a surplus or deficiency of electric charge on a capacitor. The cell no longer needed a local feedback loop to defend its state. It needed one storage node, one capacitor connected to a reference electrode, and one field-effect transistor that temporarily connected that node to a bit line.

$$Q_s = C_s(V_s - V_p)$$

where $Q_s$ is the charge associated with the storage node, $C_s$ is the storage capacitance, $V_s$ is the storage-node voltage, and $V_p$ is the capacitor's other-plate voltage. The logical label assigned to either charge state depends on the circuit convention; the physical distinction is that two resolvable storage-node conditions encode the two possible bit values.

The Bit Moves from a Feedback Loop into Stored Charge architectural comparison: active-device state versus a sampled physical quantity MULTI-TRANSISTOR LATCH CELL state maintained by regenerative feedback CROSS-COUPLED ACTIVE DEVICES the loop is the storage mechanism several active devices occupy every cell and remain connected as a bistable circuit large cell area limits bits per substrate DENNARD'S CHARGE CELL state represented by capacitor charge bit line word line one FET switch C_s reference plate the capacitor is the storage mechanism one transistor controls both writing and interrogation through the bit line minimum cell hardware raises bit density The simplification is representational: circuit state becomes stored charge. fewer devices follow because the capacitor replaces the cell's local regenerative loop

## 2. One Transistor Performs Both Operations, but It Does Not Hold the Bit

Dennard's patent, filed July 14, 1967 and issued June 4, 1968 as U.S. Patent 3,387,286, explicitly contrasted its approach with conventional field-effect memories built from a plurality of transistors in a latch configuration. In the one-transistor embodiment, the access transistor's gate connects to a word line, one current terminal connects to a bit line, and the other connects directly to the storage capacitor. Turning the word line on opens a temporary electrical path for writing or interrogation; turning it off isolates the storage node. The transistor therefore controls access to the bit, but the transistor is not itself the bit's storage medium.

Two Charge States, Reached Through the Same Access Device the word line grants access; the capacitor preserves the resulting node condition WRITE ONE CHARGE STATE bit line FET ON WL asserted Q stored 1. drive the bit line to the selected level 2. assert WL and establish storage-node charge 3. lower WL and isolate the capacitor AFTER WL FALLS the access path is gone, but Q remains temporarily WRITE THE OTHER CHARGE STATE bit line FET ON WL asserted Q' stored the same transistor and capacitor are reused only the driven bit-line condition changes the resulting Q and Q' encode opposite values NO LOCAL LATCH the cell preserves a physical quantity, not feedback One access device writes either state; neither state requires a transistor latch. the price of this density is that isolation is imperfect and the charge must later be refreshed

The two stored conditions are not permanent equilibria. Real isolation leaks, so $Q_s$ drifts after the word line turns off. That is why this architecture is *dynamic*: peripheral circuitry must periodically sense and restore the charge. Step 2 identifies the bargain without yet solving its consequences—Dennard removed the local latch and its device area, then accepted time-dependent charge loss as a system responsibility.

## 3. Why the Simplification Changes the Scale of Memory Rather Than Merely Its Schematic

A latch cell spends several transistors on preserving each bit locally. Repeating that active circuit across an array consumes substrate area, extends word and sense lines, and limits how many cells fit on one integrated-circuit substrate. Dennard's patent made cell minimization the central architectural result: one transistor could control both capacitor charging during writing and capacitor interrogation during reading. The same cell intersection could therefore be selected by a word line and reached through a bit line without carrying a complete bistable circuit at every bit location.

This is the connection to the process pieces the project has already established. The 1962 MOSFET series supplied the voltage-controlled field-effect switch; the 1967 silicon-gate series supplied the self-aligned MOS process capable of packing repeated gates and junctions tightly. Dennard's contribution was to assign those pieces a different job. The MOSFET would no longer participate in a local logic feedback network. It would become a momentary access gate to charge stored on a separate capacitive node.

The architectural economy is therefore exact, not rhetorical: remove the cell's regenerative latch, represent the bit by $Q_s=C_s(V_s-V_p)$, and reuse one access transistor for both write and read paths. What remains unresolved is how that transistor should be connected and controlled so millions of cells can share word and bit lines without disturbing one another. Step 3 builds that access device as the gate between the array and the stored charge.

Take dram 1968 store bit as capacitor charge not transistor latch further

Ask the copilot about this term, or have our engineers assess it against your process.

Ask CFSGPT about this → Request a technical assessment → Open the CFS app