DRAM 1968 Build Access Transistor Self Aligned Gate Process

# Build the Access Transistor Using the Self-Aligned Gate Process Just Completed: A Direct Reuse of 1967's Silicon-Gate Process

## 1. The New Memory Architecture Does Not Require a New Kind of Transistor

Dennard's charge-storage cell needs a gate-controlled electrical doorway, and the self-aligned silicon-gate process this project completed in 1967 already supplies exactly that device. The thin gate oxide, patterned polysilicon gate, and source/drain regions formed against the gate's own edges create a MOS transistor whose channel is opened and closed by voltage on the gate. In logic, that transistor connected one stage to the next. In this memory cell, the same structure becomes an access transistor: one diffusion connects to the column bit line, the other becomes the storage node, and the polysilicon gate extends along the row as the word line.

The fabrication sequence is reused without changing its governing geometry. Grow the gate dielectric, deposit and pattern polysilicon, and then introduce the source/drain dopant while the gate itself masks the channel. The source and drain therefore register to the gate edge by construction rather than by a second alignment. What changes is the circuit assignment placed on the finished terminals.

Reuse the 1967 Self-Aligned Sequence, Then Rename the Terminals the process module is inherited; its role changes from logic switch to cell-access gate 1 · PATTERN POLY GATE poly-Si future WL gate width defines channel before junctions exist 2 · FORM SELF-ALIGNED JUNCTIONS gate masks channel junction edges follow gate edges no new alignment term 3 · ASSIGN DRAM TERMINALS WORD LINE BIT LINE STORAGE NODE same MOS structure new memory function 1967 process inheritance: patterned gate first → self-aligned junctions second 1968 circuit reassignment: gate = WL · one diffusion = BL · other diffusion = storage node

## 2. The Word Line Selects a Row; the Transistor Connects One Cell to a Shared Bit Line

The access transistor is useful because it has two sharply different roles. With the word line unselected, its channel conductance must be very small, leaving the storage node electrically isolated from the long column bit line. With the word line selected, its channel conductance rises and the transistor couples those two nodes strongly enough to write charge into the capacitor or later let stored charge influence the bit line.

$$G_{access} \approx 0 \quad \text{for an unselected word line}, \qquad G_{access} > 0 \quad \text{for a selected word line}$$

During a write, a first-order model treats the selected transistor as an on-resistance $R_{on}$ charging the storage capacitance $C_s$ toward the driven bit-line voltage:

$$V_s(t)=V_{BL}+\left[V_s(0)-V_{BL}\right]e^{-t/(R_{on}C_s)}$$

This equation makes the division of labor precise. The bit line supplies the requested electrical condition, the word line controls when the path exists, and the capacitor retains the resulting charge after the word line removes that path.

One Selected Word Line Opens One Cell onto Its Column array-level role of the self-aligned access transistor SHARED BIT LINE FET OFFFET ONFET OFF WL 0 · unselectedWL 1 · selectedWL 2 · unselected isolated chargeselected C_s exchanges chargeisolated charge WL selects the row · BL carries the column signal · the access FET joins them only at one cell every unselected transistor must remain off so its capacitor does not share charge with the column

## 3. Self-Alignment Matters Here for Density and Isolation, Not Only Switching Speed

The 1967 silicon-gate series introduced self-alignment to remove the registration margin and parasitic overlap that limited MOS logic. A repeated memory array inherits those benefits, but gives them a new consequence. Every unnecessary micrometer in the gate-to-junction geometry is repeated once per bit; every poorly controlled junction edge risks either excess capacitance on the bit line or an unintended leakage path from the storage node. A gate that defines its own adjacent junction boundaries therefore improves both array density and the electrical separation on which charge storage depends.

This step does not yet build the capacitor. It establishes the three-terminal access structure that the capacitor will attach to: the word-line gate above the channel, the bit-line diffusion on one side, and the storage-node diffusion on the other. The device is physically familiar because the process is inherited directly from the project's completed silicon-gate work, yet functionally new because one side terminates at a node whose charge must survive after the channel disappears.

Step 3 therefore closes a deliberate reuse loop across the project: the self-aligned MOS transistor developed for faster and denser logic becomes the selectable boundary of a memory cell. Step 4 now builds the component that turns the storage-node diffusion into memory—the MOS capacitor beside the transistor.

Take dram 1968 build access transistor self aligned gate process further

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