DRAM-1968 Step 13 Confront the External Refresh Burden Before Automation

# Confront the External Refresh Burden This Cell Creates, Before Any Chip Automates It

Step 6 set a refresh interval as a cell-level timing requirement; at this series' own 1968 chronology, nothing inside the device enforces that interval — the obligation falls entirely on whatever system surrounds the chip.

## 1. State Exactly What the System Must Now Do

A 1T1C array with no on-chip refresh logic places three distinct obligations on the system designer that this series' Step 6 timing requirement makes unavoidable: a timer that fires reliably within the measured retention window, an address sequencer that steps through every row the array contains, and arbitration logic that interrupts normal read/write access long enough to let each refresh cycle complete without corrupting an in-flight operation. None of this logic exists inside the chip this series has built; all of it exists on the board, or in a dedicated support chip, external to the memory itself.

Confront the External Refresh Burden This Cell Creates, Before Any Chi Step 13 — dram-1968 State Exactly What the System Must Now Do see Section 1 Recognize This as an Open, Not Yet Resolved, Pro see Section 2 Name the Cost of Leaving It External see Section 3 THREE-PART ARGUMENT, ONE STEP dram-1968 extension, step 13 of this project's DRAM lineage

## 2. Recognize This as an Open, Not Yet Resolved, Problem

This series does not resolve that burden — doing so here would duplicate work this project's own `dram64k_1979` series does later, at a generation where pin-count pressure and row-wide activation make on-chip refresh automation specifically worth building (see that series' own Step 5). At this series' 1968 vantage point, the honest statement is that the obligation exists, is fully external, and is a direct, unavoidable consequence of the retention-and-leakage physics Steps 5 through 7 already established — not a separate design flaw layered on top of them.

Step 13 in the Dram-1968 Lineage what this step inherits and what it hands forward, by name Step 13 this step Inherits prior steps Hands Off named thread NO CELL-PHYSICS OR ARCHITECTURE RE-ARGUED each step adds a distinct angle; none re-derive settled prior content

## 3. Name the Cost of Leaving It External

An externally refreshed array spends board area, system timing budget, and a share of total memory bandwidth on refresh traffic that a logic-only system (built from static latches, as Step 1 distinguished) never needs to pay at all. That cost is the direct price of the density advantage Step 8 measured. This series states the price honestly here, and leaves its eventual on-chip resolution to the later series where that resolution actually belongs.

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