Bl Cap Trim

The BL cap trim is a secondary, targeted etch applied to the SiN cap sitting on top of the bitline stack after the main stack etch has already finished, adjusting that cap's final height or critical dimension to a specific target rather than simply accepting whatever height the stack etch happened to leave behind. This is the bitline module's version of the same CD-correction philosophy the resist trim applies much earlier in the flow — a feature comes out of its primary forming etch close to target but not exact, and a short, controlled secondary etch finishes the correction rather than demanding the primary etch hit the number perfectly on its own.

Why a separate trim step exists at all comes down to the same problem that forced a dedicated hard-mask open strategy onto the rest of this flow — a four-material stack etch has enough variables already, and asking it to also deliver perfect cap-height precision on top of clean sidewalls through every material transition is more than one recipe can reliably guarantee. Splitting the job into a primary etch that gets the stack roughly right and a secondary trim that finishes the cap's exact height gives each step a narrower, more achievable target, the same division-of-labor logic that shows up repeatedly across this DRAM flow wherever one etch's demands would otherwise be stacked on top of another's.

The spacer and air-gap modules that follow inherit whatever height this trim actually delivers, which is why consistency across the wafer matters more here than in an isolated, one-off trim. The nitride-oxide-nitride bitline spacer deposits conformally over whatever cap height is presented to it, and the air-gap removal etch downstream depends on a predictable starting geometry to clear the sacrificial material cleanly without over- or under-etching — a BL cap trim that lands inconsistently from cell to cell doesn't just leave a cosmetic height variation, it hands every downstream module a slightly different starting condition to work from.

This etch runs on the same tool families used for the bitline stack etch immediately before it, typically as a short, separately timed or endpoint-controlled step within the same overall process sequence rather than a fully independent tool run. Lam Research and Tokyo Electron platforms qualified for the multi-material bitline stack already have the plasma control needed for a brief, targeted nitride trim, so DRAM process integration treats the stack etch and the cap trim as two closely sequenced stages of one module rather than two separately scheduled operations.

Read the BL cap trim through a *divide-the-precision-budget* lens rather than a *finishing-touch* lens — the point isn't fixing a mistake from the stack etch, it's deliberately not asking that etch to deliver more precision than it reasonably can, and routing the last bit of accuracy through a step built specifically to provide it.