Cell Sti Etch

The cell STI etch cuts the shallow trench isolation that electrically separates one DRAM cell's active area from its neighbor, and inside the array this trench has to be narrower and more aggressively high-aspect-ratio than the equivalent isolation trench anywhere in the periphery, because cell pitch leaves almost no lateral room to spare. Shallow trench isolation sounds like a mature, solved process from outside DRAM, but the cell array version of it is a genuinely harder etch than its name suggests — narrow enough to fit between active lines spaced at the tightest pitch anywhere on the die, yet still deep enough to fully isolate adjacent cells electrically.

Loading between the cell array and the periphery is the specific problem that makes this etch its own distinct challenge rather than a shared recipe with ordinary isolation elsewhere on the die. The periphery's STI trenches are wider and shallower because periphery transistors aren't packed anywhere near as tightly, and a single plasma etch recipe run across a wafer with both dense, narrow cell trenches and wide, sparse periphery trenches side by side will naturally etch them at different rates — more open area around a wide trench supplies more reactive species to that trench than the crowded, narrow cell array can access, a pattern-density effect called etch loading that has to be specifically compensated for so the cell trenches reach their target depth without over-etching the periphery ones.

The pad nitride strip that follows this etch is doing more than simple cleanup. After the trench is etched and filled, the pad nitride layer that protected the active silicon during the etch gets stripped, usually in hot phosphoric acid, and how cleanly that strip removes the nitride without attacking the surrounding oxide fill directly affects the surface the active area presents to every later cell-module etch — a residue or over-etch left behind at this stage can quietly shift active area width in a way that doesn't show up until transistor electrical characteristics are measured generations of process steps later.

STI oxide recess is the step that decides how the finished trench interacts with everything built on top of it. Recessing the trench fill slightly below the silicon surface — by a wet or dry etch tuned to a specific target depth — sets a step height that later structures, including the buried wordline trench and saddle fin geometry that depend on knowing exactly where the active silicon edge sits, are built relative to; this is why cell STI etch, pad oxide/nitride strip, and STI oxide recess function as one closely coupled sequence rather than three independent steps, with high-aspect-ratio silicon etch platforms from Lam Research, Applied Materials, and Tokyo Electron tuned specifically to the cell array's loading conditions to hold that whole sequence to target.

Read cell STI through a *tightest-pitch-on-the-die* lens rather than a *routine-isolation* lens — this is the same isolation concept used across the entire chip industry, but inside a DRAM array it runs up against the single tightest geometric constraint anywhere on the die, which is exactly why it needs its own dedicated recipe instead of simply reusing whatever isolation etch already works everywhere else.