DRAM Etch Applications

A modern 6F² buried-wordline DRAM cell runs through more than fifty named etch applications before a single bit can be stored, and nearly all of them exist to solve one problem: cramming a transistor, a buried gate, and a tall capacitor into the smallest repeating cell geometry in the industry. Names and exact sequencing differ between Samsung, SK hynix, and Micron — SK hynix's saddle-fin buried wordline, Samsung's deep-trench-free stacked cell, and Micron's own BCAT (buried-channel-array-transistor) integration all solve the same problems with different etch orderings — but the module list below, organized front-end to back-end, holds across all three.

The capacitor module is the natural centerpiece of the whole flow, since the storage-node hole etch and the wet mold dip-out that follows it are the two steps most likely to determine whether a given array survives to test.

Patterning and hard-mask etches set the pitch everything downstream has to inherit. BARC and DARC open clear the anti-reflective layers so the resist pattern transfers cleanly; a hard-mask or amorphous-carbon-layer (ACL) open then locks that pattern into a layer that survives the etches below; the mandrel etch, spacer etch, and mandrel pull form the core of self-aligned double- and quadruple-patterning (SADP/SAQP), the only way to hit cell pitches finer than a single exposure can resolve; a line-cut or "chop" etch breaks continuous SADP/SAQP lines into discrete features; a photoresist trim thins the remaining resist for CD control; a hard-mask strip (ash plus wet clean) removes the now-spent mask; and alignment-key opens cut overlay marks deep enough to survive every later CMP and deposition step.

Active-area and isolation etches carve the footprint each transistor and capacitor will sit inside. The active-line etch defines the long active-area lines before they're cut; an active-cut etch chops them into individual cell islands; the cell shallow-trench-isolation (STI) trench etch — typically an HBr/Cl2/O2 chemistry tuned for a smooth, bow-free sidewall — isolates adjacent cells at the tightest pitch in the whole die; a separate periphery STI trench etch, run at a different depth and CD since peripheral transistors are larger, isolates the logic; an STI oxide recess pulls the fill oxide back below the active surface after CMP; and a pad-oxide/pad-SiN strip clears the screen oxide and nitride hard mask that protected the active area during the trench work.

Buried wordline (BCAT) etching puts the access transistor's gate underground, which is what lets the 6F² cell be as small as it is. A wordline hard-mask open sets the trench location; the wordline trench etch cuts down into the active silicon between source and drain; a saddle-fin recess etches a 3D fin profile at the trench bottom so the gate wraps three sides of the channel instead of one, raising drive current without adding footprint; a wordline metal recess (typically W or TiN) etches the buried gate metal back below the silicon surface so it doesn't short to the bitline contact above; a wordline poly recess does the same for any poly fill used in older or hybrid stacks; and a wordline cap etch-back finishes the insulating cap that seals the buried gate before the bitline contact is cut through it.

Bitline contact and bitline etching have to land precisely on top of a buried gate without touching it. The bitline contact or direct-contact (BLC/DC) etch is one of the tightest self-aligned-contact etches in the cell, landing in the narrow window between two buried wordlines; a BLC poly recess trims the contact plug; the bitline stack etch patterns the bitline conductor itself (commonly W-on-poly or an all-metal stack); a separate peripheral gate (BG) etch patterns the larger logic-side gates in the same general module; a bitline spacer etch insulates the bitline sidewalls; an air-gap spacer removal etches away a sacrificial spacer material to leave a low-k air gap between bitlines, cutting parasitic capacitance; and a bitline cap trim finishes the bitline's insulating cap.

Storage-node contact and landing-pad etching reach from the active area up to where the capacitor will sit, through the densest part of the whole cell. A storage-node-contact (SNC) fence etch cuts the insulating fence that keeps adjacent storage-node contacts from shorting to each other at pitch; the storage-node-contact or buried-contact (BC) etch itself lands on the active area between wordlines; an SNC poly recess trims that plug; a landing-pad (LP) etch patterns the enlarged pad that gives the capacitor below more contact area than the contact pitch alone would allow; and a landing-pad gap-fill etch-back plananrizes the insulator between pads without touching the pads themselves.

The capacitor module holds what the industry generally agrees are the hardest etches in DRAM, because capacitance has to keep rising as cell area keeps shrinking. A mold hard-mask open sets the pattern for the tall sacrificial mold stack; the storage-node hole or cylinder etch then bores through that mold at an aspect ratio of 50:1 or higher — deeper, relative to its width, than almost any other etch in semiconductor manufacturing, and the single biggest yield risk in the whole flow since any bow, twist, or neck closes off the hole before it reaches bottom; a support-structure open cuts lateral tie-bars between adjacent cylinders so they don't topple once the mold is removed; the mold dip-out, a wet etch using HF or LAL (a buffered LAL/BOE-type chemistry) rather than a plasma step, dissolves the sacrificial mold oxide and leaves free-standing cylinders held up only by the support structure; a bottom-electrode separation etch isolates each cylinder's bottom electrode from its neighbors after a conformal electrode deposition; a top-electrode or plate etch patterns the shared top electrode that covers the whole array; and a capacitor contact (PC) etch finally reaches down through the finished capacitor module to tie the plate to the periphery.

Periphery and middle-of-line etching build the logic that reads and writes the array, using more conventional CMOS steps. A peripheral gate spacer etch insulates the logic transistor gates; a peripheral source/drain contact etch lands on the diffusion; a deep metal contact or M0C etch reaches from the first metal layer down past the taller array topology; strap contacts periodically tie the buried wordline to an overlying metal strap so resistance doesn't dominate wordline delay across a long row; and a silicide-block, SAB, or RPO (resist-protect-oxide) etch masks off areas that should not form silicide, protecting sensitive junctions during the silicidation anneal.

Back-end etching finishes the die the same way it would on any other logic-adjacent chip. An M1 trench etch and via etch build the first interconnect levels; an aluminum metal etch patterns the thicker top-level pad metal while a Cu-damascene etch/fill sequence handles the finer lower levels; a fuse-window open exposes electrical or laser fuses used for redundancy and repair; and passivation/pad opens plus a polyimide open finish the top of the die for wire bonding or bumping.

HBM and advanced-packaging etches extend the same DRAM die vertically instead of just laterally. A through-silicon-via (TSV) etch — typically a Bosch-process SF6/C4F8 cycle that alternates etch and passivation steps to hold a straight sidewall through hundreds of microns of silicon — opens the vertical connection between stacked dies; a TSV liner open clears the insulating liner at the via bottom so the fill metal can contact the layer below; a backside-reveal etch thins the wafer from behind after stacking and bonding; a backside passivation open exposes the TSV from the thinned side; and bump/RDL (redistribution-layer) etching patterns the fan-out wiring and bump pads that connect the finished HBM stack to its base logic die.

A long tail of supporting and auxiliary etches keeps every module above from failing in ways that don't show up until test. A bevel etch controls edge delamination and particle generation at the wafer's outer rim; pre-clean and dry-clean steps run ahead of nearly every critical etch to remove native oxide and surface contamination; a post-etch polymer clean strips the passivation byproducts that plasma etches leave behind, especially after the high-aspect-ratio capacitor and TSV steps; rework strips remove a failed pattern so the wafer can be re-processed instead of scrapped; test-key and scribe-line opens cut the in-line electrical test structures and die-separation streets; and a backside film strip clears temporary carrier-wafer films used during thin-wafer handling for HBM.

Emerging 4F² vertical-channel-transistor (VCT) and 3D DRAM designs are already adding a new etch vocabulary on top of this one, because moving the access transistor vertical is the next move once buried wordlines and tall capacitors run out of room to shrink: a vertical-channel pillar etch replaces the planar BCAT transistor with a standing pillar; a buried-bitline trench etch moves the bitline below the array instead of above it; a Si/SiGe superlattice stack etch patterns the layered channel material these designs are built from; a lateral selective SiGe recess etches sacrificial SiGe out from between silicon layers to leave suspended channels, conceptually the DRAM cousin of 3D NAND's SiN pull-back; and a staircase etch — borrowed directly from 3D NAND — lands contacts on stacked word lines once the array itself goes vertical.

Read as one list, the roughly fifty-plus etch applications above are really four repeating problems wearing Samsung-, SK hynix-, and Micron-specific names: pattern a transistor and a buried gate into the smallest active area the industry builds, land a self-aligned contact in the gap between two gates without shorting either one, bore and release a 50:1-aspect-ratio capacitor that has to hold its shape once the mold is gone, and — for HBM — punch straight through the finished die to stack another one on top, which is why buried-wordline etch, bitline-contact etch, storage-node hole etch, and mold dip-out are the four steps that actually gate DRAM yield.