Top Electrode Etch

The top electrode etch is the step that caps off a DRAM cell capacitor by patterning the TiN or SiGe plate layer draped over every storage node cylinder in the array, cutting it into the array-edge boundary each die actually needs while leaving the capacitor's internal electrical connection completely untouched.

Node separation done
Bottom electrodes isolated per cell
High-k dielectric deposited
ZrO2/Al2O3/ZrO2 (ZAZ), conformal ALD
Top electrode deposited
TiN or SiGe, blankets whole array
Plate/edge etch
Cuts array boundary, not individual cells
Plate contact landed
Single shared bias connection

This etch is a boundary cut, not a separation cut, and that distinction is the whole point. Unlike the node separation etch that comes immediately before it — which has to isolate thousands of individually addressed bottom electrodes from one another — the top electrode is deliberately left as one continuous shared sheet across the entire array, because every cell's capacitor returns to the same fixed bias plate rather than to its own private node. The only cutting this step actually does is trim that shared plate back at the array's outer edge and over support-structure openings, so the plate etch's job is topological cleanup at the perimeter, not per-cell isolation, and getting that distinction backwards would short the array in exactly the way node separation was built to prevent.

TiN and SiGe solve different problems and foundries pick based on which constraint is tighter. Titanium nitride gives a lower work function and cleaner ALD step coverage into the deep, narrow spaces between storage node cylinders, which matters more as cell height climbs past roughly 1-1.5 microns at advanced nodes; doped silicon-germanium can deposit with less mechanical stress on the fragile, support-bridge-only cylinder array left behind by the earlier mold dip-out, which matters more when yield loss is coming from physical cylinder collapse rather than electrical leakage. Samsung, SK hynix, and Micron have each published variations on both schemes, and the choice tracks each company's specific capacitor aspect ratio and prior dielectric stack rather than any industry-wide consensus.

Top Electrode Plate: Interior vs Edge Cut one continuous sheet inside the array, trimmed only at the boundary cross-section, three adjacent cells top electrode, continuous over interior high-k dielectric (green) on each isolated bottom electrode (brown cylinder) plate etch cuts here, array edge periphery shared plate bias contact lands once, serves every cell under it one plate, billions of capacitors, one trimmed boundary the array stays one shared electrode by design — the etch's job is the edge, not the interior

TiN and SiGe produce physically different plate cross-sections, and the choice shows up directly in how the film sits over the cylinder tops.

TiN vs SiGe Top Electrode Fill same cylinder geometry, different stress and step coverage TiN plate conformal ALD step coverage lower work function, tight gaps preferred at tall aspect ratios SiGe plate lower mechanical stress gentler on fragile, support-only cylinder arrays post dip-out each foundry picks per its own aspect ratio and stack

Getting this etch wrong produces a failure mode that looks electrical but is actually geometric. If the plate etch doesn't fully clear the trim region, a stray bridge of TiN or SiGe left at the array boundary can connect the plate to an adjacent periphery structure that was supposed to stay isolated, and the resulting leakage path shows up in test as a retention or standby-current failure — the same kind of root-cause misdiagnosis the node separation etch's incomplete isolation case produces, just at the opposite end of the capacitor module. Because the plate sits directly over the fragile, support-bridge-only cylinder array, the etch chemistry also has to be gentle enough not to undercut or topple cylinders near the cut line, which is why foundries lean on the same high-aspect-ratio dielectric and metal etch-back platforms from Lam Research and Applied Materials already qualified earlier in the capacitor module rather than introducing a new chemistry just for this one boundary trim.

Read through a shared-plate lens, this etch is the capacitor module's closing move: the one deliberately un-isolated layer in a module otherwise obsessed with isolating every cell from every other cell.

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