TSV Backside Reveal

The TSV backside reveal etch has to stop exactly at a target that isn't sitting at a known, fixed depth the way almost every prior endpoint in this project has — the buried tip of each via-last TSV varies in its exact depth from die to die and wafer to wafer, so this etch is thinning bulk silicon down toward a statistically distributed target rather than a single known material interface, with real failure modes on both sides of landing correctly. After TSVs are etched and filled from the front side late in the back-end flow, the wafer gets mounted to a carrier and ground down mechanically from the back until it's only tens of micrometers thick, and a final etch then removes the remaining silicon with enough precision to expose the buried copper TSV tips without leaving some of them still capped under a thin residual layer of silicon while simultaneously controlling how far those exposed tips protrude or recede relative to the new backside surface.

Silicon-to-copper etch selectivity has to be extremely high here, which is a genuinely different selectivity demand from the TSV liner open etch covered in the previous round. That earlier etch had to treat one single insulating film completely differently depending on its location within the same via; this etch instead has to remove one material — bulk silicon — almost everywhere while barely touching a completely different material — the copper TSV fill and its liner — wherever the two happen to meet, which is a selectivity problem between two chemically distinct materials rather than a directional-selectivity problem within one film; getting that ratio wrong either leaves silicon residue capping some TSVs (no electrical access after bonding) or etches into the copper itself and damages the via's electrical integrity right at the one point where it has to make contact with the next die in the stack.

Protrusion and recess control is the actual engineering target here, not a simple binary exposed-or-not outcome, which echoes the fuse window etch's residual-thickness philosophy from earlier in this project but applies it to a metal tip height instead of a dielectric thickness. A TSV tip that protrudes too far above the new backside surface risks mechanical damage or uneven contact pressure when the next die in the stack gets bonded on top of it; a tip that sits too recessed below the surface can fail to make reliable electrical and mechanical contact at all during that same bonding step — so the target isn't just "expose the copper," it's landing within a specific protrusion height window across every TSV on the wafer simultaneously, despite each via's actual depth varying slightly from its neighbors.

This step exists for a purpose with no equivalent anywhere else in this project: enabling an electrical and mechanical connection to a completely different, separately manufactured die stacked on top of this one. Every etch covered before this round connected one layer of a single die to another layer of that same die; the TSV backside reveal is explicitly preparing a surface where a second die's own TSVs or bump structures will land and bond, which is why HBM stacks can reach eight, twelve, or more layers high — each die's backside reveal step is the physical handoff point where one die's internal interconnect stack meets the next die's, repeated once per layer in the finished stack.

Read through a statistical-target lens, the TSV backside reveal etch is where this project's etch endpoints stop being fixed geometric targets and start being distributions this etch has to land inside across an entire wafer simultaneously — not because the process lost precision, but because the thing it's etching toward was never placed at one single depth to begin with.