DRAM 64k 1979 Ras Cas Timing Sequencing Requirement

# Tell the Chip Which Half of the Address It Is Looking At

## 1. Add the Signal the Multiplexing Scheme Was Missing

Step 1 showed that the same 8 pins can carry a row address and then a column address, halving the pin count a 64K-bit array would otherwise need. That scheme as stated has a gap: nothing on those 8 pins distinguishes a row address from a column address. Voltage levels on an address pin look identical whether they mean "row 37" or "column 37" — the meaning is a matter of timing convention, not of anything electrically visible on the pin itself. Two additional control pins carry that missing meaning: the Row Address Strobe ($\overline{RAS}$) and the Column Address Strobe ($\overline{CAS}$), each a single active-low pulse that tells the chip's internal address latches which half of the two-part address currently sits on the shared pins.

$$\overline{RAS}\downarrow:\ \text{latch present pins as row address},\qquad \overline{CAS}\downarrow:\ \text{latch present pins as column address}$$

This is the minimum signaling this architecture needs: two pins added back to recover the unambiguous addressing that Step 1's pin-sharing scheme gave up implicitly. The net pin budget is still a win — Step 1 saved 8 address pins, and this step spends back only 2 to make the scheme workable — but the win is not free of a new requirement Step 1 did not need to state: the two strobes must arrive in the correct order, with the correct timing relationship to the data they latch.

Two Strobes Restore the Meaning Pin-Sharing Removed voltage on an address pin alone cannot say whether it means row or column 8 SHARED ADDRESS PINS — SAME SIGNAL, AMBIGUOUS MEANING ALONE RAS pin: row strobe CAS pin: column strobe two pins spent RAS↓ = "latch this as row" CAS↓ = "latch this as column" 8 pins saved (Step 1) − 2 pins spent here = 6 net pins saved STILL A NET WIN — BUT NOW A TIMING-ORDER REQUIREMENT EXISTS RAS must arrive, settle, and be followed correctly by CAS — a sequencing rule Step 1 never needed how much margin does that ordering actually need? Section 2 derives the timing relationship directly

## 2. Derive the Timing Margin the Sequencing Rule Actually Requires

The row address cannot simply be followed immediately by the column address; the array needs time to act on the row address before the column address becomes meaningful. Asserting $\overline{RAS}$ selects an entire row and begins the sense-amplifier process that reads every cell along that row simultaneously — this takes a finite settling time $t_{RAS,min}$ for the sense amplifiers to resolve a reliable signal. Only after that settling time has elapsed does asserting $\overline{CAS}$ productively narrow the selection down to one column within the now-active row:

$$t_{RCD}\ge t_{RAS,min},\qquad t_{RCD}=t_{\overline{CAS}\downarrow}-t_{\overline{RAS}\downarrow}$$

$t_{RCD}$ — the RAS-to-CAS delay — is not a design nicety; it is a hard lower bound set by how fast the array's own sense amplifiers can resolve a row's worth of stored charge into a clean logic signal. Asserting $\overline{CAS}$ too early, before $t_{RAS,min}$ has elapsed, risks latching a column address against a row selection that has not yet stabilized, which can read or write the wrong cell. This connects directly to work this project has already done: the sense-amplifier settling behavior $t_{RAS,min}$ depends on is the same charge-sharing physics the 1968 series derived for a single cell's read operation, now aggregated across an entire row read simultaneously.

CAS Must Wait for the Row's Sense Amplifiers to Settle Real Diagram — the timing diagram this sequencing rule actually produces RAS↓ sense amps settling — t_RAS,min CAS↓ (valid, after settle) CAS too early → unreliable selection t_RCD t_RCD ≥ t_RAS,min a hard lower bound set by sense-amplifier settling, not a design preference the same charge-sharing physics 1968's series derived for one cell, now applied to a whole row t_RAS,min sets the chip's minimum cycle time a direct tradeoff against the access speed the system wants — Section 3

## 3. Connect the Timing Cost to the Pin Savings Step 1 Claimed, and Set Up Step 3

This step completes the honest accounting Step 1's pin-count win deserves. Halving the address pin count was not a free simplification — it was a trade of pin area for timing margin, and this step quantifies what that margin actually costs: a minimum RAS-to-CAS delay set by physics this project already derived in 1968, now governing an entire memory cycle's floor rather than a single cell's read. A system designer choosing a 64K DRAM over a wider, non-multiplexed alternative is explicitly accepting $t_{RAS,min}$ as a speed penalty in exchange for the package-size and pin-count savings Step 1 quantified.

This also reveals a question Step 1's simplified picture glossed over: the row address Step 1 described as selecting "which row" actually drives every sense amplifier along that row simultaneously, which means the multiplexing scheme this series is building is not purely an addressing convenience — it structurally couples to how the array's read operation itself unfolds. Step 3 takes up that coupling directly: what the row-select operation this step's timing depends on actually does to every cell in the selected row, and why that full-row activation, not just the addressing scheme sitting on top of it, is the mechanism this entire generation's refresh strategy will come to depend on.

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